Quad aware locking primitive

• US 7,979,617 B2
• Filed: 11/04/2008
• Issued: 07/12/2011
• Est. Priority Date: 12/28/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jackson, Benedict, Rockhold, Ronald L., Rajamony, Ramakrishnan, McKenney, Paul E.
• Primary Examiner(s): Rinehart; Mark
• Assistant Examiner(s): Huynh; Kim T
• Application Number:
  US12/264,764
• Publication Number:
  US 20090063826A1
• Time in Patent Office: 980 Days
• Field of Search: 710/200, 710240-244, 710260-269
• US Class Current: 710/200
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.

Claims

1. A computer system comprising:

multiple processors;

a lock selected from the group consisting of;

an interruptible lock, and a lock which waits using only local memory; and

a hierarchical representation of processor organization; and

a lock primitive for processing the lock responsive to the hierarchy, wherein said primitive further comprises a handoff flag to grant a lock to a processor requesting an unconditional lock from a processor requesting a conditional lock.

2. The computer system of claim 1, wherein said primitive further comprises a conditional lock acquisition primitive.

3. The computer system of claim 2, wherein said conditional lock acquisition further indicates a lock failure if said lock is not immediately available.

4. The computer system of claim 1, wherein said primitive further comprises an unconditional lock acquisition primitive.

5. The computer system of claim 1, wherein said primitive further comprises a primitive for an unconditional release of said lock.

6. A computer system comprising:

multiple processors;

a lock selected from the group consisting of;

an interruptible lock, and a lock which waits using only local memory;

a hierarchical representation of processor organization; and

a lock primitive for processing the lock responsive to the hierarchy, wherein said primitive further comprises a release flag to prevent races between acquisition and release of the lock.

7. The computer system of claim 6, wherein said primitive further comprises a conditional lock acquisition primitive.

8. The computer system of claim 7, wherein said conditional lock acquisition further indicates a lock failure if said lock is not immediately available.

9. The computer system of claim 6, wherein said primitive further comprises an unconditional lock acquisition primitive.

10. The computer system of claim 6, wherein said primitive further comprises a primitive for an unconditional release of said lock.

11. An article comprising:

a computer-readable signal bearing medium;

multiple processors;

means in the medium for hierarchically organizing at least some of the processors of a computer system;

means in the medium for providing a lock selected from the group consisting of;

an interruptible lock, and a lock which waits using only local memory; and

means in the medium for processing the lock responsive to the hierarchy, wherein said means is a release flag responsive to races between acquisition and release of a lock.

12. The article of claim 11, wherein the means is a conditional lock acquisition primitive.

13. The article of claim 11, wherein the means is an unconditional lock acquisition primitive.

14. The article of claim 11, wherein a spin stage is entered by a processor if the lock is not immediately available.

15. The article of claim 11, wherein the means is an unconditional lock release primitive.

16. An article comprising:

a computer-readable signal bearing medium;

multiple processors;

means in the medium for hierarchically organizing at least some of the processors of a computer system;

means in the medium for providing a lock selected from the group consisting of;

an interruptible lock, and a lock which waits using only local memory; and

means in the medium for processing the lock responsive to the hierarchy, wherein said means is a handoff flag responsive to a processor requesting an unconditional lock from a processor requesting a conditional lock.

17. The article of claim 16, wherein the means is a conditional lock acquisition primitive.

18. The article of claim 16, wherein the means is an unconditional lock acquisition primitive.

19. The article of claim 16, wherein a spin stage is entered by a processor if the lock is not immediately available.

20. The article of claim 16, wherein the means is an unconditional lock release primitive.