Memory array search engine

• US 7,979,667 B2
• Filed: 12/10/2007
• Issued: 07/12/2011
• Est. Priority Date: 12/10/2007
• Status: Active Grant

• Current Assignee: Valley Device Management
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Allen, Walter, France, Robert
• Primary Examiner(s): Krofcheck; Michael C
• Application Number:
  US11/953,501
• Publication Number:
  US 20090150646A1
• Time in Patent Office: 1,310 Days
• Field of Search: None
• US Class Current: 711/203
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 16/90339 by using parallel associative memories or content-addressable memories
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

Systems and/or methods that facilitate a search of a memory component(s) to locate a desired logical block address (LBA) associated with a memory location in a memory component are presented. Searches to locate a desired LBA(s) in a memory component(s) associated with a processor component are offloaded and controlled by the memory component(s). A search component searches pages in the memory array to facilitate locating a page of data associated with an LBA stored in the memory component. The search component can retrieve a portion of a page of data in a block in the memory component to facilitate determining whether the page contains an LBA associated with a command based in part on command information. The search component can search pages in the memory component until a desired page is located or a predetermined number of searches is performed without locating the desired page.

Claims

1. A system that facilitates access of at least one memory, comprising:

the at least one memory that contains a plurality of memory locations to facilitate storage of data;

a search component that searches the at least one memory and locates a logical block address associated with a memory location of the plurality of memory locations based in part on a data pattern associated with a command;

a sensor component that detects data values of data stored in a portion of a page in the at least one memory array;

a register component that receives data detected by the sensor component, the register component manipulates the data so that the data is in a proper order in the register component based in part on offset information associated with the command; and

a mask component that receives the data, as manipulated, from the register component and masks non-determinate bits of the data to a known value.

2. The system of claim 1, further comprising:

at least one memory array that is located in the at least one memory, the plurality of memory locations are situated in the at least one memory array; and

a controller component that receives the command and provides control information to the search component to facilitate control of the search by the search component to locate the logical block address.

3. The system of claim 2, the search component searches for a logical block address in at least one of an entire portion of the at least one memory or focuses the search for the logical block address to a region in the at least one memory that is less than the entire portion of the at least one memory.

4. The system of claim 2, the controller component focuses a search for the logical block address in the at least one memory to begin at a particular place in the at least one memory based in part on the command, wherein the command contains at least one of information that identifies the at least one memory, block identification information, block offset information, page offset information, page area offset information, logical block address information, a data pattern, search termination information, or search order information, or a combination thereof.

5. The system of claim 2, the at least one memory array contains a predetermined number of blocks, and the logical block address is located within a page of a plurality of pages contained within a block in the at least one memory array.

6. The system of claim 5, the search component retrieves only a portion of a page that contains a data pattern associated with the logical block address.

7. The system of claim 1, further comprising:

a comparator component that receives the data pattern associated with the command and receives the data from the mask component and compares the data pattern to determinate bits of the data to determine whether the determinate bits of the data match the data pattern and indicates whether there is a match; and

a buffer component that receives a page containing a logical block address specified in the command, wherein the controller component facilitates retrieval of the page containing the logical block address specified in the command based in part on information from the comparator component that indicates the determinate bits of the data of the page match the data pattern, the controller component provides the page to the buffer component.

8. The system of claim 1, further comprising:

a processor component that generates commands and facilitates execution of operations in the at least one memory, and generates at least one command to facilitate a search of the at least one memory, wherein the at least one memory is comprised of more than one memory, each memory comprises a respective search component, wherein the processor component generates and provides commands to each respective memory and the respective search component of each respective memory locates the respective logical block address in the respective memory, and a respective controller component of a respective memory provides an indicator signal to the processor component that indicates that at least one of a respective logical block address is located, a page associated with the respective logical block address is loaded, the search of the respective memory is complete, and the search of the respective memory is terminated.

9. The system of claim 8, wherein searches for respective logical block addresses in the respective memories are interleaved such that the searches in respective memories are performed in parallel.

10. The system of claim 1, the search component searches through pages in the at least one memory until the logical block address specified in the command is located or until a predetermined maximum number of searches has been performed based in part on search termination information associated with the command.

11. An electronic device comprising the system of claim 1.

12. The electronic device of claim 11, the electronic device is one of a computer, a cellular phone, a digital phone, a video device, a smart card, a personal digital assistant, a television, an electronic game, a digital camera, an electronic organizer, an audio player, an audio recorder, an electronic device associated with digital rights management, a Personal Computer Memory Card International Association (PCMCIA) card, a trusted platform module (TPM), an electronic control unit associated with a motor vehicle, a global positioning satellite (GPS) device, an electronic device associated with an airplane, an electronic device associated with an industrial control system, a Hardware Security Module (HSM), a set-top box, a secure memory device with computational capabilities, or an electronic device with at least one tamper-resistant chip.

13. A method that facilitates accessing at least one memory, comprising:

comparing a subset of information received from a portion of a page in the at least one memory to a data pattern based in part on a command; and

loading the page associated with the subset of information when the subset of information matches the data pattern to facilitate accessing the at least one memory;

sensing data values of data stored in a portion of a page, the portion of a page from which data is sensed is determined based in part on offset information;

loading the data that is stored;

manipulating the data so that the data is in a proper order in a register component based in part on the offset information and

masking non-determinate bits of the manipulated data to a known value.

14. The method of claim 13, further comprising:

aligning the data, the aligning the data comprising at least one of shifting the data or rotating the data; and

loading the data to facilitate comparison of the data with the data pattern.

15. The method of claim 14, further comprising:

loading the data pattern to facilitate comparison of the data pattern with the data;

comparing the data to the data pattern.

16. The method of claim 15, further comprising:

at least one of;

retrieving a page associated with the data if the data matches the data pattern,

loading the page,

indicating that a logical block address associated with the page is located, and

providing the page;

or

searching for a logical block address in at least one other page in the at least one memory.

17. The method of claim 13, further comprising:

providing a first command to a first memory to facilitate a search for a first logical block address in the first memory;

providing at least one other command to at least one other memory to facilitate a search for at least one other logical block address in the at least one other memory;

locating a first page in the first memory that contains the first logical block address based in part on the first command;

locating at least one other page in the at least one other memory that contains the at least one other logical block address based in part on the at least one other command;

loading the first page;

loading the at least one other page;

indicating that the first page is ready to be transmitted;

indicating that the at least one other page is ready to be transmitted;

transmitting the first page; and

transmitting the at least one other page.

18. The method of claim 17, further comprising:

performing the locating the first page and the locating the at least one other page in parallel.

19. The method of claim 13, further comprising:

terminating a search for a logical block address in the at least one memory based in part on a predetermined maximum number of searches specified in the command.