System and method for register renaming
First Claim
1. A method for improving instruction parallelism in a microprocessor, comprising:
- fetching an instruction;
adding the fetched instruction into an instruction window;
assigning a tag to the fetched instruction, wherein the assigned tag includes bits uniquely identifying an address of a storage location in a temporary buffer where a result of the instruction in the instruction window is to be stored;
determining whether an original source register address of the fetched instruction depends upon a destination register address of a prior-fetched instruction previously stored in the instruction window;
if such dependency is determined, setting the original source register address of the fetched instruction to be a different tag, the different tag being associated with the prior-fetched instruction;
executing the fetched instruction to generate a result; and
storing the result of the fetched instruction at the storage location in the temporary buffer that corresponds to the assigned tag.
3 Assignments
0 Petitions
Accused Products
Abstract
A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.
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Citations
34 Claims
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1. A method for improving instruction parallelism in a microprocessor, comprising:
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fetching an instruction; adding the fetched instruction into an instruction window; assigning a tag to the fetched instruction, wherein the assigned tag includes bits uniquely identifying an address of a storage location in a temporary buffer where a result of the instruction in the instruction window is to be stored; determining whether an original source register address of the fetched instruction depends upon a destination register address of a prior-fetched instruction previously stored in the instruction window; if such dependency is determined, setting the original source register address of the fetched instruction to be a different tag, the different tag being associated with the prior-fetched instruction; executing the fetched instruction to generate a result; and storing the result of the fetched instruction at the storage location in the temporary buffer that corresponds to the assigned tag. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A register renaming apparatus in a microprocessor, comprising:
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an instruction window to store instructions; logic to assign one of a plurality of tags to each of the instructions as the instruction enters the instruction window, each of the plurality of tags uniquely identifying a register in a temporary buffer for storing a result of a corresponding one of the instructions in the instruction window; a data dependency checker to determine whether an instruction entering the instruction window has an input dependency on another instruction in the instruction window; and a register rename circuit to set an original source register address of an instruction having an input dependency to the tag assigned to the instruction causing the input dependency. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A register renaming circuit for a microprocessor, comprising:
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one or more comparators to compare a source register address of a new instruction in an instruction window with one or more destination register addresses of one or more old instructions in the instruction window; and a selector to select a tag associated with a one of the old instructions whose destination register address matches the source register address of the new instruction, the tag uniquely identifying a register of a temp buffer for storing a result corresponding to the new instruction in the instruction window. - View Dependent Claims (31, 32, 33, 34)
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Specification