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System and method for register renaming

  • US 7,979,678 B2
  • Filed: 05/26/2009
  • Issued: 07/12/2011
  • Est. Priority Date: 12/31/1992
  • Status: Expired due to Fees
First Claim
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1. A method for improving instruction parallelism in a microprocessor, comprising:

  • fetching an instruction;

    adding the fetched instruction into an instruction window;

    assigning a tag to the fetched instruction, wherein the assigned tag includes bits uniquely identifying an address of a storage location in a temporary buffer where a result of the instruction in the instruction window is to be stored;

    determining whether an original source register address of the fetched instruction depends upon a destination register address of a prior-fetched instruction previously stored in the instruction window;

    if such dependency is determined, setting the original source register address of the fetched instruction to be a different tag, the different tag being associated with the prior-fetched instruction;

    executing the fetched instruction to generate a result; and

    storing the result of the fetched instruction at the storage location in the temporary buffer that corresponds to the assigned tag.

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