Method to improve electrical leakage performance and to minimize electromigration in semiconductor devices

• US 7,981,483 B2
• Filed: 09/27/2007
• Issued: 07/19/2011
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: TEL Manufacturing and Engineering of America, Inc.
• Original Assignee: TEL Epion Inc. (Tokyo Electron Limited)
• Inventors: Russell, Noel, Sherman, Steven, Hautala, John J.
• Primary Examiner(s): Padgett; Marianne L
• Application Number:
  US11/863,036
• Publication Number:
  US 20090087577A1
• Time in Patent Office: 1,391 Days
• Field of Search: None
• US Class Current: 427/528
• CPC Class Codes: H01J 2237/0812 Ionized cluster beam [ICB] sources
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288

Abstract

Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices are generally described herein. Other embodiments may be described and claimed.

Claims

1. A method of forming a phosphorus-doped layer, the method comprising:

planarizing a top surface of a workpiece to form a substantially planar surface with a plurality of copper conductive paths and a plurality of dielectric regions;

infusing phosphorus dopant into and below the planarized top surface of the workpiece using a gas cluster ion beam system to form a phosphorous-doped layer from the top surface to a desired depth of about 50-200 angstroms beneath the top surface in the plurality of copper conductive paths and the plurality of dielectric regions wherein the presence of the phosphorus dopant in the phosphorous-doped layer is effective to getter metal contaminants in the plurality of dielectric regions and to minimize electromigration in the plurality of copper conductive paths; and

forming a barrier layer over the phosphorous-doped layer to minimize material transfer from the phosphorous-doped layer formed in the plurality of copper conductive paths and dielectric regions.

2. The method of claim 1, further including a pre-treatment step prior to infusing phosphorus into the planarized top surface of the workpiece.

3. The method of claim 1, wherein the phosphorous-doped layer comprises between 0.1 atomic % and 10 atomic % phosphorus dopant.

4. The method of claim 1, wherein the substantially planar surface is planarized by a chemical mechanical planarization or an electropolishing process.

5. The method of claim 1, wherein a phosphorus source comprising phosphine and a non-condensable gas is used to infuse phosphorus into the top surface of the workpiece.

6. The method of claim 5, wherein the non-condensable gas is selected from the group consisting of helium, neon, and hydrogen.

7. The method of claim 5, further including a second condensable gas source selected from the group consisting of argon, nitrogen, carbon dioxide, and oxygen.

8. The method of claim 1, wherein the barrier layer is selected from the group consisting of silicon nitride, silicon carbide, nitrogen doped silicon carbide, boron carbon nitride, and boron nitride.