Manufacturing method of thin film transistor including low resistance conductive thin films

• US 7,981,734 B2
• Filed: 07/08/2009
• Issued: 07/19/2011
• Est. Priority Date: 02/02/2006
• Status: Expired due to Fees

• Current Assignee: Casio Computer Company Limited, Kochi Industrial Promotion Center
• Original Assignee: Casio Computer Company Limited, Kochi Industrial Promotion Center
• Inventors: Ishii, Hiromitsu, Hokari, Hitoshi, Yoshida, Motohiko, Furuta, Hiroshi, Hirao, Takashi, Matsuda, Tokiyoshi, Hiramatsu, Takahiro, Furuta, Mamoru
• Primary Examiner(s): Ngo; Ngan
• Assistant Examiner(s): LIU, BENJAMIN T
• Application Number:
  US12/499,559
• Publication Number:
  US 20090269881A1
• Time in Patent Office: 741 Days
• Field of Search: 438/104, 438/151, 438/158, 438/159, 438/161, 438/479, 438/686, 438/706, 438/720, 438/722, 438/742, 438/149, 438/584, 438/585, 257/E21.411, 257/E21.256, 257/E21.31, 257/E21.37
• US Class Current: 438/149
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.

Claims

1. A manufacturing method of a thin film transistor comprising:

forming a source/drain electrode on a substrate;

forming low resistance conductive thin films on the source/drain electrode;

forming an oxide semiconductor thin film layer on the low resistance conductive thin films;

forming a first gate insulating film on the oxide semiconductor thin film layer;

etching the first gate insulating film, the low resistance conductive thin films, and the oxide semiconductor thin film layer such that (i) side surfaces of the first gate insulating films, corresponding side surfaces of the low resistance conductive thin films, and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of a channel of the thin film transistor, and (ii) a width of the first gate insulating film is wider than a width of the source/drain electrode in the channel width direction of the channel;

forming a second gate insulating film on the first gate insulating film; and

mounting a gate electrode over the second gate insulating film.

2. The method according to claim 1, wherein the oxide semiconductor thin film layer primarily comprises zinc oxide.

3. The method according to claim 1, wherein the etching is dry etching.

4. A manufacturing method of a thin film transistor comprising:

forming a gate electrode on a substrate;

forming a gate insulating film on the gate electrode and forming a source/drain electrode on the gate insulating film;

forming low resistance conductive thin films on the source/drain electrode;

forming an oxide semiconductor thin film layer on the low resistance conductive thin films;

forming a first overcoat insulating film on the oxide semiconductor thin film;

etching the first overcoat insulating film, the low resistance conductive thin films, and the oxide semiconductor thin film layer such that (i) side surfaces of the first overcoat insulating film, corresponding surfaces of the low resistance conductive thin films, and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of a channel of the thin film transistor, and (ii) a width of the first overcoat insulating film is wider than a width of the source/drain electrode in the channel width direction of the channel; and

forming a second overcoat insulating film on the first overcoat insulating film.

5. The method according to claim 4, wherein the oxide semiconductor thin film layer primarily comprises zinc oxide.

6. The method according to claim 4, wherein the etching is dry etching.

7. A manufacturing method of a thin film transistor comprising:

forming a predetermined number of pairs of source/drain electrodes, each said pair comprising a source electrode and a drain electrode defining a gap therebetween at an area corresponding to a channel of the thin film transistor, and each said pair being spaced apart from an adjacent pair by a spacing;

forming a pair of low resistance conductive thin films, which define a gap therebetween along the channel-corresponding area, such that one of the low resistance conductive thin films covers the source electrodes and another of the low resistance conductive thin films covers the drain electrodes;

forming an oxide semiconductor thin film layer on the pair of low resistance conductive thin films, on the channel-corresponding area, and on each said spacing; and

etching the oxide semiconductor thin film layer and the low resistance conductive thin films along each said spacing between adjacent pairs of the source/drain electrodes, to separate each of the oxide semiconductor thin film layer and the low resistance conductive thin films into a predetermined number of oxide semiconductor thin film layer pieces and a predetermined number of pairs of low resistance conductive thin film pieces corresponding respectively to the predetermined number of pairs of source/drain electrodes, such that at each said spacing side surfaces of each of the oxide semiconductor thin film layer pieces coincide with corresponding side surfaces of the pair of low resistance conductive thin film pieces corresponding to the oxide semiconductor thin film layer piece.

8. The method of according to claim 7, wherein the forming of the pair of low resistance conductive thin films comprises etching a low resistance conductive thin film to form the pair of low resistance conductive thin films to have outer ends that are positioned outside outer ends of a final shape of the low resistance conductive thin films.