Semiconductor device and a method of manufacturing the same

• US 7,981,747 B2
• Filed: 04/27/2009
• Issued: 07/19/2011
• Est. Priority Date: 08/04/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Shiraishi, Masaki, Nakazawa, Yoshito
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/385,979
• Publication Number:
  US 20090212358A1
• Time in Patent Office: 813 Days
• Field of Search: 438/197, 438/270, 438/289, 438/306, 438/524, 438/529, 438/530
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p⁻type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p⁻type semiconductor region is formed under a n⁺type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

Claims

1. A method of manufacturing a semiconductor device including a trench gate type MISFET,

the trench gate type MISFET comprising:

a semiconductor substrate having a main surface and a bottom surface opposite to the main surface, the semiconductor substrate having a first conductivity type;

a first semiconductor layer formed on the main surface of the semiconductor substrate, the first semiconductor layer having a top surface apart from the semiconductor substrate, the first semiconductor layer having the first conductivity type, and the first semiconductor layer acting as a drain region of the MISFET;

a trench formed on the top surface of the first semiconductor layer, a distance between the top surface of the first semiconductor layer and a bottom of the trench being not more than 1 μ

m;

a gate insulating film of the MISFET formed on an inner surface of the trench;

a gate electrode of the MISFET formed on the gate insulating film in the trench;

a channel forming region of the MISFET formed in the first semiconductor layer, the channel forming region being in contact with the trench, the bottom of the trench being positioned below a bottom of the channel forming region, and the channel forming region having a second conductivity type opposite to the first conductivity type;

a source region of the MISFET formed over the channel forming region in the first semiconductor layer;

the source region being in contact with the trench, and the source region having the first conductivity type; and

a punch through stopper region formed between the source region and channel forming region in the first semiconductor layer, the punch through stopper region having the second conductivity type, and the punch through stopper region having a higher impurity concentration than the channel forming region,

wherein the method comprising steps of;

forming the trench formed in the first semiconductor layer;

forming the gate insulating film on the trench;

forming the gate electrode of the MISFET on the gate insulating;

after the gate electrode forming step, introducing a first impurity to form the channel forming region by a first ion implantation; and

after the gate electrode forming step, introducing a second impurity to form the punch through stopper region by a second ion implantation in the channel region different from the first ion implantation such that a concentration distribution of the punch through stopper region is decided by a concentration distribution of the second ion implantation and such that the punch through stopper region has an impurity concentration relatively flat,

wherein the second impurity is diffused by heat treatment such that the channel forming region has an impurity concentration gradually decreased, in a depth direction along the trench, from an interface portion between the channel region and the punch through stopper region to an interface portion between the channel region and the semiconductor layer.

2. The method according to claim 1, wherein the second ion implantation is performed after a diffusion of the first impurity of the first ion implantation using heat treatment.

3. The method according to claim 1, wherein the first semiconductor layer is formed by an epitaxial growth method.

4. The method according to claim 1, further comprising the steps of:

forming a drain electrode on the bottom surface of the semiconductor substrate, the drain electrode being electrically connected with the semiconductor substrate and first semiconductor layer;

forming an interlayer insulating film over the gate electrode and source region;

forming a contact groove in the insulating film, a part of the source region being exposed from the contact groove; and

forming a source electrode in the contact groove, the source electrode being electrically connected with the source region.

5. A method of manufacturing a semiconductor device including a trench gate type MISFET,

the trench gate type MISFET comprising:

a semiconductor substrate having a main surface and a bottom surface opposite to the main surface, the semiconductor substrate having a first conductivity type;

a first semiconductor layer formed on the main surface of the semiconductor substrate, the first semiconductor layer having a top surface apart from the semiconductor substrate, the first semiconductor layer having the first conductivity type, and the first semiconductor layer acting as a drain region of the MISFET;

a trench formed on the top surface of the first semiconductor layer, a distance between the top surface of the first semiconductor layer and a bottom of the trench being not more than 1 μ

m;

a gate insulating film of the MISFET formed on an inner surface of the trench;

a gate electrode of the MISFET formed on the gate insulating film in the trench;

a channel forming region of the MISFET formed in the first semiconductor layer and being in contact with the trench, the bottom of the trench being positioned below a bottom of the channel forming region, and the channel forming region having a second conductivity type opposite to the first conductivity type;

a source region of the MISFET formed over the channel forming region in the first semiconductor layer;

the source region being in contact with the trench, and the source region having the first conductivity type; and

a punch through stopper region formed between the source region and channel forming region in the first semiconductor layer and being in contact with a top of the channel forming region, the punch through stopper region having the second conductivity type and having a higher impurity concentration than the channel forming region,

wherein the method comprising steps of;

forming the trench formed in the first semiconductor layer;

forming the gate insulating film on the trench;

forming the gate electrode of the MISFET on the gate insulating;

after the gate electrode forming step, introducing a first impurity to form the channel forming region by a first ion implantation; and

after the gate electrode forming step, introducing a second impurity to form the punch through stopper region by a second ion implantation in the channel region different from the first ion implantation such that a concentration distribution of the punch through stopper region is decided by a concentration distribution of the second ion implantation and such that the punch through stopper region has an impurity concentration relatively flat,

after the gate electrode forming step, diffusing the second impurity by heat treatment such that the channel forming region has an impurity concentration gradually decreased, in a depth direction along the trench, from the top of the channel region to the bottom of the channel region.

6. The method according to claim 5, wherein the first semiconductor layer is formed by an epitaxial growth method.

7. The method according to claim 5, wherein the second ion implantation is performed after the channel forming region forming.

8. The method according to claim 5, further comprising the steps of:

forming a drain electrode on the bottom surface of the semiconductor substrate, the drain electrode being electrically connected with the semiconductor substrate and first semiconductor layer;

forming an interlayer insulating film over the gate electrode and source region;

forming a contact groove in the insulating film, a part of the source region being exposed from the contact groove; and

forming a source electrode in the contact groove, the source electrode being electrically connected with the source region.