Semiconductor component and method of manufacture

• US 7,981,757 B2
• Filed: 10/11/2010
• Issued: 07/19/2011
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Shastri, Sudhama C., Burke, Peter A., Hose, Sallie
• Primary Examiner(s): MANDALA, VICTOR A
• Application Number:
  US12/902,130
• Publication Number:
  US 20110027961A1
• Time in Patent Office: 281 Days
• Field of Search: 438/171, 438/329, 438/381, 257/528, 257/E27.024, 257/E21.003
• US Class Current: 438/381
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Claims

1. A method for manufacturing a semiconductor component, comprising:

providing a substrate;

forming a first passive circuit element at a first level above the substrate, wherein forming the first passive circuit element includes forming an inductor;

forming a second passive circuit element at a second level above the first level, wherein at least one of the first or second passive circuit elements comprises a damascene structure, and wherein forming the second passive circuit element includes forming a capacitor; and

forming a third passive circuit element from or above the substrate including forming a resistor.

2. The method of claim 1, further including:

forming a first layer of dielectric material over the substrate;

forming a second layer of dielectric material over the first layer of dielectric material;

forming a third layer of dielectric material over the second layer of dielectric material, wherein at least the first and third layers of dielectric material are a different material from the second layer of dielectric material; and

forming at least one damascene opening in the first, second, and third layers of dielectric material.

3. The method of claim 2, further including forming at least one of copper or aluminum in the at least one damascene opening.

4. The method of claim 2, wherein forming the at least one damascene opening includes forming at least first and second damascene openings, wherein the first damascene opening exposes a portion of the resistor and further including forming at least one of copper or aluminum in the first and second damascene openings.

5. The method of claim 4, further including:

forming a first conductor over the at least one of copper or aluminum disposed in at least the second damascene opening;

forming a fourth layer of dielectric material over the first conductor; and

forming a second conductor over the fourth layer of dielectric material, wherein the first and second conductors comprise aluminum and wherein the first conductor is electrically connected to the at least one of copper or aluminum disposed in at least the second damascene opening.

6. The method of claim 5, further including

forming a third damascene opening in the third layer of dielectric material;

forming a conductive material in the third damascene opening;

forming a passivation layer over the at least one of copper or aluminum in the at least one damascene opening and over the conductive material in the third damascene opening; and

exposing the conductive material in the third damascene opening.

7. A method for manufacturing a semiconductor component, comprising:

forming an inductor using a damascene process, the inductor formed in a first vertical planar region; and

forming a capacitor in a second vertical planar region, the capacitor having a first conductor separated from a second conductor by a dielectric material, wherein the first vertical planar region is below the second vertical planar region.

8. The method of claim 7, wherein forming the capacitor comprises:

forming a first layer of aluminum, the first layer of aluminum serving as the first conductor;

forming a layer of silicon nitride on the first layer of aluminum; and

forming a second layer of aluminum on the layer of silicon nitride, the second layer of aluminum serving as the second conductor.

9. The method of claim 8, wherein the second layer of aluminum contacts the inductor.

10. The method of claim 9, further including forming the inductor from a metal selected from the group of metals comprising copper and aluminum.

11. The method of claim 7, wherein forming the capacitor comprises:

forming a first layer of aluminum, the first layer of aluminum serving as the first conductor;

forming a layer of silicon nitride on the first layer of aluminum; and

forming a second layer of aluminum on the layer of silicon nitride, the second layer of aluminum serving as the second conductor and wherein the first layer of aluminum contacts the inductor.