TFT substrate and method for manufacturing TFT substrate

• US 7,982,215 B2
• Filed: 10/02/2006
• Issued: 07/19/2011
• Est. Priority Date: 10/05/2005
• Status: Expired due to Fees

• Current Assignee: Idemitsu Kosan Company Limited
• Original Assignee: Idemitsu Kosan Company Limited
• Inventors: Tanaka, Nobuo, Inoue, Kazuyoshi, Yano, Koki
• Primary Examiner(s): Louie; Wai-Sing
• Assistant Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US12/089,260
• Publication Number:
  US 20100127253A1
• Time in Patent Office: 1,751 Days
• Field of Search: 257/223, 257/291, 257/443, 257/43, 257/59, 257/E29.296, 257/E21.19, 257/E33.019, 257/E21.476, 438/104
• US Class Current: 257/43
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 2201/50 Protective arrangements
• CPC Class Codes: G02F 2203/09 transflective
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate includes: a substrate; a gate electrode and a gate wire formed above the substrate; a gate insulating film formed above the gate electrode and the gate wire; a first oxide layer formed above the gate insulating film which is formed at least above the gate electrode; and a second oxide layer formed above the first oxide layer; wherein at least a pixel electrode is formed from the second oxide layer.

Claims

1. A TFT substrate comprising:

a substrate;

a gate electrode and a gate wire formed above the substrate;

a gate insulating film formed at least above the gate electrode and the gate wire;

a first oxide layer formed above the gate insulating film which is formed at least above the gate electrode; and

a second oxide layer formed above the first oxide layer;

wherein at least a pixel electrode is formed from the second oxide layer, and wherein at least one of the following conditions of a) or b) or c) or d) must be satisfied;

a) the pixel electrode, a source electrode and a drain electrode, and a source wire and a drain wire are formed from the second oxide layer;

or

b) the pixel electrode is formed of the first oxide layer and the second oxide layer;

or

c) the TFT substrate is provided with a protective insulating film above the gate electrode and the gate wire, as well as above the source wire, the drain wire, the source electrode and the drain electrode, in a state in which the pixel electrode, the source/drain wire pad and the gate wire pad are exposed, and the source wire, the drain wire, the source electrode, the drain electrode and the pixel electrode are formed from the second oxide layer.

2. A method for producing a TFT substrate according to claim 1, comprising the steps of:

forming a gate electrode and a gate wire above a substrate using a first mask;

stacking a gate insulating film, a first oxide layer, a second oxide layer and a resist in this order above the substrate, the gate electrode and the gate wire;

forming the resist in a predetermined shape by half-tone exposure using a second mask;

selectively etching the first oxide layer and the second oxide layer to form a source wire, a drain wire and a pixel electrode;

reforming the resist in a predetermined shape;

selectively etching the second oxide layer to form a source electrode, a drain electrode and a channel part; and

selectively etching the gate insulating film to form a gate insulating pad.

3. A method for producing a TFT substrate according to claim 1, comprising the steps of:

forming a gate electrode and a gate wire above a substrate using a first mask;

stacking a gate insulating film, a first oxide layer, a second oxide layer and a resist in this order above the substrate, the gate electrode and the gate wire;

forming the resist in a predetermined shape by half-tone exposure using a second mask;

etching the first oxide layer and the second oxide layer and the gate insulating film to form a source wire, a drain wire, a pixel electrode and a gate wire pad;

reforming the resist in a predetermined shape; and

selectively etching the second oxide layer to form a source electrode, a drain electrode and a channel part.

4. A method for producing a TFT substrate according to claim 1, comprising the steps of:

forming a gate electrode and a gate wire on a substrate using a first mask;

stacking a gate insulating film, a first oxide layer, a second oxide layer and a second resist in this order on the substrate, the gate electrode and the gate wire, and forming the second resist in a predetermined shape using a second mask;

patterning the second oxide layer by an etching method using the second resist to form a source wire, a drain wire, a source electrode, a drain electrode and a pixel electrode;

stacking a protective insulating film and a third resist in this order on the first oxide layer, the source wire, the drain wire, the source electrode, the drain electrode and the pixel electrode, and forming the third resist in a predetermined shape by half-tone exposure;

patterning the protective insulating film and the first oxide layer on the gate wire pad by an etching method using the third resist; and

after reforming the third resist, selectively patterning the protective insulating film on the pixel electrode and the source/drain wire pad, as well as the gate insulating film on the gate wire pad by an etching method using the third resist to expose the pixel electrode, the source/drain wire pad, and the gate wire pad.

5. A method for producing a TFT substrate according to claim 1, comprising the steps of:

forming a gate electrode and a gate wire on a substrate using a first mask;

stacking a gate insulating film, a first oxide layer, a second oxide layer, an auxiliary conductive layer and a second resist in this order on the substrate, the gate electrode and the gate wire, and forming the second resist in a predetermined shape by half-tone exposure;

patterning the auxiliary conductive layer and the second oxide layer by an etching method using the second resist to form a source wire, a drain wire, a source electrode, a drain electrode and a pixel electrode, as well as an auxiliary wire and an auxiliary electrode formed of the auxiliary conductive layer;

after reforming the second resist, selectively patterning the auxiliary conductive layer on the pixel electrode by an etching method using the second resist to expose the pixel electrode;

stacking a protective insulating film and a third resist in this order on the first oxide layer and the pixel electrode, as well as on the auxiliary conductive layer formed on the source wire, the drain wire, the source electrode and the drain electrode, and forming the third resist in a predetermined shape by half-tone exposure;

patterning the protective insulating film and the first oxide layer on the gate wire pad by an etching method using the third resist; and

after reforming the third resist, selectively patterning the protective insulating film on the pixel electrode and the source/drain wire pad, as well as the gate insulating film on the gate wire pad by an etching method using the third resist to expose the pixel electrode, the source/drain wire pad and the gate wire pad.

6. A method for producing a TFT substrate according to claim 1, comprising the steps of:

forming a gate electrode and a gate wire above a substrate using a first mask;

stacking a gate insulating film, a first oxide layer, a second oxide layer and a second resist above the substrate, the gate electrode and the gate wire, and forming the second resist in a predetermined shape by half-tone exposure;

patterning the second oxide layer and the first oxide layer by an etching method using the second resist to form a source wire, a drain wire, and a pixel electrode;

after reforming the second resist, selectively patterning the second oxide layer above the gate electrode by an etching method using the second resist to form a source electrode and a drain electrode;

stacking a protective insulating film and a third resist above the exposed gate insulating film and the exposed first oxide layer, as well as above the source wire, the drain wire, the source electrode, the drain electrode and the pixel electrode, and forming the third resist in a predetermined shape using the third mask; and

patterning the protective insulating film above the pixel electrode and the source/drain wire pad, as well as the protective insulating film and the gate insulating film above the gate wire pad by an etching method using the third resist to expose the pixel electrode, the source/drain wire pad and the gate wire pad.

7. A method for producing a TFT substrate according to claim 1, comprising the steps of:

forming a gate electrode and a gate wire on a substrate using a first mask;

stacking a gate insulating film, a first oxide layer, a second oxide layer, an auxiliary conductive layer and a second resist above the substrate, the gate electrode and the gate wire, and forming the second resist in a predetermined shape by half-tone exposure;

patterning the auxiliary conductive layer, the second oxide layer and the first oxide layer by an etching method using the second resist to form a source wire, a drain wire, a source electrode and a pixel electrode, as well as an auxiliary wire formed of the auxiliary conductive layer;

after reforming the second resist, selectively patterning the auxiliary conductive layer and the second oxide layer above the gate electrode by an etching method using the second resist to form a source electrode and a drain electrode, as well as an auxiliary electrode formed of the auxiliary conductive layer;

stacking a protective insulating film and a third resist above the exposed gate insulating film and the exposed first oxide layer, as well as above the auxiliary conductive layer formed above the source wire, the drain wire, the source electrode, the drain electrode and the pixel electrode, and forming the third resist in a predetermined shape using a third mask; and

patterning the protective insulating film above the pixel electrode and the source/drain wire pad, as well as the protective insulating film above the gate wire pad by an etching method using the third resist to expose the auxiliary conductive layer above the pixel electrode and the source/drain wire pad;

patterning the exposed auxiliary conductive layer above the pixel electrode and the source/drain wire pad by an etching method using the third resist to expose the pixel electrode and the source/drain wire pad; and

patterning the gate insulating film above the gate wire pad by an etching method using the third resist to expose the gate wire pad.

8. A method for producing a TFT substrate according to claim 1, comprising the steps of:

forming a gate electrode and a gate wire above a substrate using a first mask;

stacking a gate insulating film, a first oxide layer, a second oxide layer, a reflective metal layer and a second resist above the substrate, the gate electrode and the gate wire, and forming the second resist in a predetermined shape by half-tone exposure;

patterning the reflective metal layer, the second oxide layer and the first oxide layer by an etching method using the second resist to form a source wire, a drain wire and a pixel electrode;

after reforming the second resist, selectively patterning the reflective metal layer and the second oxide layer above the gate electrode by an etching method using the second resist to form a source electrode and a drain electrode;

stacking a protective insulating film and a third resist above the exposed gate insulating film and the exposed first oxide layer, as well as above the reflective metal layer formed above the source wire, the drain wire, the source electrode, the drain electrode and the pixel electrode, and forming the third resist in a predetermined shape by half-tone exposure;

exposing part of the pixel electrode using the third resist and forming a reflective metal part formed of the reflective metal layer;

reforming the third resist in a predetermined shape; and

patterning the protective insulating film above the reflective metal part and the source/drain wire pad, as well as the protective insulating film and the gate insulating film above the gate wire pad by an etching method to expose the reflective metal part and the source/drain wire pad and the gate wire pad.

9. The method for producing a TFT substrate according to claim 2, wherein the selective etching of the first oxide layer and the second oxide layer is performed by an etching method A in which the etching rates of the first oxide layer and the second oxide layer are faster than the etching rate of the gate insulating film;

the selective etching of the second oxide layer is performed by an etching method B in which the etching rate of the second oxide layer is faster than the etching rates of the first oxide layer and the gate insulating film, and

the selective etching of the gate insulting film is performed by an etching method C in which the etching rate of the gate insulating film is faster than the etching rates of the first oxide layer and the second oxide layer.

10. The method for producing a TFT substrate according to claim 2, further comprising the step of forming an auxiliary wire or an auxiliary electrode above the source wire, the drain wire, the source electrode and the drain electrode using a third mask.

11. The method for producing a TFT substrate according to claim 2, wherein the first oxide layer is an n-type oxide semiconductor layer and the second oxide layer is an oxide conductor layer.

12. The method for producing a TFT substrate according to claim 8, further comprising the step of forming, above the reflective metal layer, an oxide conductor layer for protecting the metal layer for protecting the reflective metal layer.

13. The method for producing a TFT substrate according to claim 10, wherein the step of forming the auxiliary wire or the auxiliary electrode is a step where an auxiliary wire layer or an auxiliary electrode layer is patterned by an etching method using a third mask after etching properties of the first oxide layer and the second oxide layer are changed by heat treatment.

14. A TFT substrate comprising:

a substrate;

a gate electrode and a gate wire formed above the substrate;

a gate insulating film formed at least above the gate electrode and the gate wire;

a first oxide layer formed above the gate insulating film which is formed at least above the gate electrode; and

a second oxide layer formed above the first oxide layer;

wherein pixel electrode, a source electrode and a drain electrode, and a source wire and a drain wire are formed from the second oxide layer.

15. The TFT substrate according to claim 14, wherein the first oxide layer is patterned by an etching method A in which the etching rates of the first oxide layer and the second oxide layer are faster than the etching rate of the gate insulating film and is formed of a material which has resistance to an etching method B in which the etching rate of the second oxide layer is faster than the etching rates of the first oxide layer and the gate insulating film;

the second oxide layer is formed of a material which can be etched by the etching method A and the etching method B; and

the gate insulating film is patterned by an etching method C in which the etching rate of the gate insulating film is faster than the etching rates of the first oxide layer and the second oxide layer and is formed of a material which has resistance to the etching method A and the etching method B.

16. The TFT substrate according to claim 14, wherein an auxiliary wire or an auxiliary electrode is formed on the source electrode, the drain electrode, the source wire and the drain wire.

17. The TFT substrate according to claim 14, wherein the first oxide layer is an n-type oxide semiconductor layer and the second oxide layer is an oxide conductor layer.

18. The TFT substrate according to claim 15, wherein an auxiliary wire or an auxiliary electrode is formed on the source electrode, the drain electrode, the source wire and the drain wire, the first oxide layer and the second oxide layer have resistance to the etching method B of claim 3, and the auxiliary wire and the auxiliary electrode are patterned by the etching method B.

25. The TFT substrate according to claim 14, wherein the energy gaps of the first oxide layer and the second oxide layer are 3.0 eV or more.

19. A TFT substrate comprising:

a substrate;

a gate electrode and a gate wire formed above the substrate;

a gate insulating film formed at least above the gate electrode and the gate wire;

a first oxide layer formed above the gate insulating film which is formed at least above the gate electrode; and

a second oxide layer formed above the first oxide layer;

wherein at least a pixel electrode is formed from the second oxide layer;

and the pixel electrode is formed of the first oxide layer and the second oxide layer.

20. A TFT substrate comprising:

a substrate;

a gate electrode and a gate wire formed above the substrate;

a gate insulating film formed at least above the gate electrode and the gate wire;

a first oxide layer formed above the gate insulating film which is formed at least above the gate electrode; and

a second oxide layer formed above the first oxide layer;

wherein at least a pixel electrode is formed from the second oxide layer;

and the TFT substrate is provided with a protective insulating film above the gate electrode and the gate wire, as well as above the source wire, the drain wire, the source electrode and the drain electrode, in a state in which the pixel electrode, the source/drain wire pad and the gate wire pad are exposed, and the source wire, the drain wire, the source electrode, the drain electrode and the pixel electrode are formed from the second oxide layer.

21. The TFT substrate according to claim 20, wherein the first oxide layer is an n-type oxide semiconductor layer and the second oxide layer is an oxide conductor layer.

22. The TFT substrate according to claim 20, wherein the pixel electrode is formed of a stacked film of the first oxide layer and the second oxide layer.

23. The TFT substrate according to claim 20, wherein the first oxide layer is formed at least on the side facing the substrate of the second oxide layer.

24. The TFT substrate according claim 20, wherein an auxiliary conductive layer is formed on at least one of the source wire, the drain wire, the source electrode, the drain electrode and the pixel electrode.

26. A TFT substrate comprising:

a substrate;

a gate electrode and a gate wire formed above the substrate;

a gate insulating film formed at least above the gate electrode and the gate wire;

a first oxide layer formed above the gate insulating film which is formed at least above the gate electrode; and

a second oxide layer formed above the first oxide layer;

wherein at least a pixel electrode is formed from the second oxide layer;

and at least the pixel electrode and a source/drain electrode which is connected with the pixel electrode are formed from the second oxide layer wherein the TFT substrate is provided with a protective insulating film above the gate electrode and the gate wire, as well as above the source wire, the drain wire, the source electrode and the drain electrode, in a state in which the pixel electrode, the source/drain wire pad and the gate wire pad are exposed, and the source wire, the drain wire, the source electrode, the drain electrode and the pixel electrode are formed from the second oxide layer.

27. The TFT substrate according to claim 26, wherein the upper part of the TFT substrate is covered by the protective insulating film and the protective insulating film has openings at positions corresponding to each of the pixel electrode, the source/drain wire pad and the gate wire pad.

28. The TFT substrate according to claim 26, wherein the first oxide layer is an n-type oxide semiconductor layer and the second oxide layer is an oxide conductor layer.

29. The TFT substrate according to claim 26, wherein the pixel electrode is formed of a stacked film of the first oxide layer and the second oxide layer.

30. The TFT substrate according to claim 26, wherein the first oxide layer is formed at least on the side facing the substrate of the second oxide layer.

31. The TFT substrate according to claim 26, wherein an auxiliary conductive layer is formed above at least one of the source wire, the drain wire, the source electrode, the drain electrode and the pixel electrode.

32. The TFT substrate according to claim 26, wherein the first oxide layer is formed at a predetermined position corresponding to the channel part, the source wire, the drain wire, the source electrode, the drain electrode, and the pixel electrode.

33. The TFT substrate according to claim 26, wherein the energy gap of the first oxide layer and/or the second oxide layer is 3.0 eV or more.

34. The TFT substrate according to claim 26, wherein part of the pixel electrode is covered by a reflective metal layer.

35. The TFT substrate according to claim 26, wherein the TFT substrate is provided with a metal layer and has an oxide conductor layer for protecting the metal layer.

36. the TFT substrate according to claim 26, wherein the TFT substrate is provided with at least one of the gate electrode, the gate wire, the source wire, the drain wire, the source electrode, the drain electrode and the pixel electrode, and at least one of the gate electrode, the gate wire, the source wire, the drain wire, the source electrode, and the drain electrode and the pixel electrode is formed of an oxide transparent conductive layer.

37. The TFT substrate according to claim 34, wherein at least one of the source wire, the drain wire, the source electrode and the drain electrode is formed from the reflective metal layer.

38. The TFT substrate according to claim 34, wherein the reflective metal layer is formed of a thin film of aluminum, silver or gold, or of an alloy layer containing aluminum, silver or gold.