Multiple gate transistor architecture providing an accessible inner source-drain node

• US 7,982,243 B1
• Filed: 05/04/2007
• Issued: 07/19/2011
• Est. Priority Date: 05/05/2006
• Status: Expired due to Fees

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Li, Jason Yuxin, Iversen, Christian Rye
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US11/744,536
• Time in Patent Office: 1,537 Days
• Field of Search: 257192-195, 257202-206, 257368-369, 257/E29.12, 257/E29.246, 257/401
• US Class Current: 257/202
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/8124 with multiple gate

Abstract

The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain structure having multiple drain fingers, which extend from a drain bus. The fingers of the respective source and drain structures are interleaved wherein a meandering path is formed between the source and drain structures. Two or more gate structures run substantially parallel to one another along the meandering path between the source and drain structures. An SD structure is provided between each adjacent pair of gate structures and runs along the meandering path to form the SD node. An SD extension is coupled to the SD structure and accessible by other circuitry to allow a signal to be applied to the SD structure during operation.

Claims

1. A multiple gate transistor comprising:

a source structure having a plurality of source fingers extending from a source bus;

a drain structure having a plurality of drain fingers extending from a drain bus and interleaved with the plurality of source fingers wherein a meandering path is formed between the source and drain structures;

a plurality of gate structures that are substantially parallel with one another and extend along the meandering path between the source and drain structures;

a source-drain structure that extends along the meandering path between adjacent ones of the plurality of gate structures to form a source-drain node, wherein the source-drain structure is continuous along the meandering path; and

a source-drain extension that is electrically connected to the source-drain structure and externally accessible to facilitate electrical connections to associated circuitry, wherein at least one signal from the associated circuitry is applied to the source-drain node via the source-drain extension.

2. The multiple gate transistor of claim 1 wherein the source-drain structure is between the adjacent ones of the plurality of gate structures.

3. The multiple gate transistor of claim 1 wherein the plurality of gate structures comprises N gate structures, there are N−

1 source-drain structures such that each of the N−

1 source-drain structures is provided between an adjacent pair of the N gate structures, and N is an integer greater than 2.

4. The multiple gate transistor of claim 1 wherein the source structure, the drain structure, and the plurality of gate structures form a multiple gate field effect transistor (FET).

5. The multiple gate transistor of claim 1 wherein the source structure, the drain structure, and the plurality of gate structures form a multiple gate pseudomorphic high-electron mobility transistor (pHEMT).

6. The multiple gate transistor of claim 1 wherein the source structure, the drain structure, and the plurality of gate structures form a multiple gate metal oxide semiconductor field-effect transistor (MOSFET).

7. The multiple gate transistor of claim 1 wherein the source structure, the drain structure, and the plurality of gate structures form a multiple gate metal semiconductor field-effect transistor (MESFET).

8. The multiple gate transistor of claim 1 wherein each of the source structure, the drain structure, and the plurality of gate structures is electrically coupled to the associated circuitry.

9. The multiple gate transistor of claim 1 wherein the meandering source-drain structure forms a virtual source-drain node.

10. The multiple gate transistor of claim 1 wherein:

the meandering path comprises a first end; and

the source drain extension is externally accessible from the first end.

11. The multiple gate transistor of claim 10, further comprising:

wherein the meandering path comprises a second end; and

a second source drain extension that is electrically connected to the source-drain structure and is externally accessible to facilitate electrical connection to associated circuitry from the second end of the meandering path.

12. The multiple gate transistor of claim 11, wherein where there are no external connections to the source-drain structure along the meandering path.