Package in package semiconductor device

• US 7,982,298 B1
• Filed: 12/03/2008
• Issued: 07/19/2011
• Est. Priority Date: 12/03/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Jae Dong, Yang, Sung Jin, Kang, Dae Byoung, Ok, Jung Tae
• Primary Examiner(s): Lee; Eugene
• Assistant Examiner(s): Gumedzoe; Peniel M
• Application Number:
  US12/327,763
• Time in Patent Office: 958 Days
• Field of Search: 257/621, 257/686, 257/777, 257/E23.116, 257/E23.123, 257/E23.124, 257/E23.126, 257/E23.194, 257/E25.006, 257/E25.013, 257/E25.018, 257/E25.021, 257/E25.027
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19107 : off-chip wires

Abstract

In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In certain embodiments, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. One or more of the semiconductor dies may include through-silicon vias formed therein for facilitating the electrical connection thereof to the conductive pattern of the substrate or to other electronic components within the vertical stack. Similarly, the semiconductor package may be provided with through-mold vias to facilitate the electrical connection thereof to other electronic components within the vertical stack. In other embodiments of the present invention, a semiconductor die which is electrically connected to the conductive pattern of the substrate is encapsulated with an inner package body which itself is formed to include through-mold vias used to facilitate the electrical connection thereof to another semiconductor die stacked thereon. In each embodiment of the semiconductor device, the vertically stacked electronic components thereof may be covered with a package body which also partially covers the substrate.

Claims

1. A semiconductor device, comprising:

a substrate having an electrically conductive pattern formed thereon;

a first semiconductor die having a plurality of through-silicon vias formed therein and electrically connected to the conductive pattern of the substrate; and

a semiconductor package having a plurality of through-mold vias formed therein and electrically connected to the through-silicon vias of the first semiconductor die.

2. The semiconductor device of claim 1 further comprising a plurality of solder halls electrically connected to the conductive pattern of the substrate.

3. The semiconductor device of claim 1 further comprising a second semiconductor die positioned between the first semiconductor die and the semiconductor package, the second semiconductor die having a plurality of through-silicon vias formed therein and electrically connected to the through-silicon vias of the first semiconductor die and the through-mold vias of the semiconductor package.

4. The semiconductor device of claim 3 further comprising a package body which covers at least portions of the substrate, the first semiconductor die, the second semiconductor die and the semiconductor package.

5. The semiconductor device of claim 4 further comprising a third semiconductor die electrically connected to the semiconductor package and exposed in the package body.

6. The semiconductor device of claim 1 further comprising a package body which covers at least portions of the substrate, the first semiconductor die and the semiconductor package.

7. A semiconductor device comprising:

a substrate having an electrically conductive pattern formed thereon;

a first semiconductor die having a plurality of through-silicon vias formed therein and electrically connected to the conductive pattern of the substrate;

a second semiconductor die electrically connected to the through-silicon vias of the first semiconductor die, the first semiconductor die being disposed between the substrate and the second semiconductor die;

a semiconductor package attached to the second semiconductor die, the first and second semiconductor dies being disposed between the substrate and the semiconductor package;

at least one conductive wire electrically connecting the semiconductor package to the conductive pattern of the substrate; and

a package body at least partially encapsulating the substrate, the first semiconductor die, the second semiconductor die, the semiconductor package and the conductive wire.

8. The semiconductor device of claim 7 further comprising a plurality of solder halls electrically connected to the conductive pattern of the substrate.

9. A semiconductor device, comprising:

a substrate having an electrically conductive pattern formed thereon;

a first semiconductor die electrically connected to the conductive pattern of the substrate;

an inner package body at least partially covering the first semiconductor die and the substrate, the inner package body having a plurality of through-mold vias formed therein and electrically connected to both the conductive pattern of the substrate and the first semiconductor die;

a second semiconductor die electrically connected to the through-mold vias of the inner package body; and

a package body which encapsulates at least portions of the inner package body, the second semiconductor die and the substrate.

10. The semiconductor device of claim 9 wherein the first semiconductor die is electrically connected to the conductive pattern of the substrate through the use of at least one conductive wire which is covered by the inner package body.

11. The semiconductor of claim 9 wherein the first semiconductor die is electrically connected to the conductive pattern of the substrate through the use of conductive bumps which are covered by the inner package body.

12. The semiconductor device of claim 9 further comprising a third semiconductor die which is interposed between the inner package body and the second semiconductor die and is at least partially encapsulated by the package body, the third semiconductor die having a plurality of through-silicon vias formed therein which are electrically connected to the through-mold vias of the inner package body and to the first second semiconductor die.

13. A semiconductor device, comprising:

a substrate having an electrically conductive pattern formed thereon;

a first semiconductor die electrically connected to the conductive pattern of the substrate;

a semiconductor package having a plurality of through-mold vias firmed therein and electrically connected to the first semiconductor die; and

a package body which encapsulates at least portions of the substrate, the first semiconductor die, and the semiconductor package.

14. The semiconductor device of claim 13 wherein the semiconductor package includes an inner semiconductor die which is electrically connected to the first semiconductor die by the through-mold vias of the semiconductor package.

15. The semiconductor device of claim 13 wherein at least a portion of the semiconductor package is exposed within the package body.

16. The semiconductor device of claim 13 further comprising a second semiconductor die positioned between and electrically connected to the first semiconductor die and the through-mold vias of the semiconductor package, the second semiconductor die being at least partially encapsulated by the package body.

17. A semiconductor device, comprising:

a substrate having an electrically conductive pattern formed thereon;

a first semiconductor die electrically connected to the conductive pattern of the substrate;

an inner package body at least partially covering the first semiconductor die and the substrate, the inner package body having a plurality of through-mold vias formed therein and electrically connected to both the conductive pattern of the substrate and the first semiconductor die;

a second semiconductor die electrically connected to the through-mold vias of the inner package body; and

a third semiconductor die interposed between the inner package body and the second semiconductor die, the third semiconductor die having a plurality of through-silicon vias formed therein which are electrically connected to the through-mold vias of the inner package body and to the second semiconductor die.

18. The semiconductor device of claim 17 further comprising a package body which covers at least portions of the first and second semiconductor dies, the inner package body, and the substrate.