Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines

• US 7,983,065 B2
• Filed: 04/08/2009
• Issued: 07/19/2011
• Est. Priority Date: 04/08/2009
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Samachisa, George
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US12/420,334
• Publication Number:
  US 20100259960A1
• Time in Patent Office: 832 Days
• Field of Search: 365/51, 365/130, 365/135, 365/154, 365/180, 365/182, 365/230.01, 365/230.07
• US Class Current: 365/51
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/5614 using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/19 Memory cell comprising at least a nanowire and only two terminals
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/78 Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 : between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/24 : based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 : the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8822 : Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 : Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/884 : Other compounds of groups 13-15, e.g. elemental or compound semiconductors
• CPC Class Codes: H10N 70/8845 : Carbon or carbides

Abstract

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Claims

1. A data memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having orthogonal x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, the memory further comprising:

a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array in the x and y-directions,

a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the first plurality of conductive lines in the individual planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes,

a plurality of non-volatile re-programmable memory elements elongated in the z-direction through the plurality of planes and individually connected between the first and second conductive lines adjacent the crossings thereof at the plurality of locations, and

a plurality of select devices arranged to individually connect selected ones of the plurality of first conductive lines to selected ones of a plurality of third conductive lines.

2. The memory of claim 1, wherein

the third conductive lines are elongated in the y-direction,

the select devices are arranged to make those of the first conductive lines aligned in the y-direction connectable with selected ones of the plurality of third conductive lines, and

a plurality of control lines extending in the x-direction and individually connected with a plurality of the select devices aligned in the x-direction to enable connection of a plurality of first conductive lines aligned in the x-direction with different ones of the third conductive lines.

3. The memory of either one of claim 1 or 2, wherein the plurality of select devices and the plurality of third conductive lines are formed in a semiconductor substrate and the plurality of planes are formed as a stack over the semiconductor substrate.

4. The memory of claim 3, wherein the individual memory elements are characterized by including a material that reversibly changes its level of electrical conductance between at least first and second stable levels in response to an electrical stimulus being applied through the first and second conductive lines between which the memory element is connected.

5. The memory of claim 1, wherein the individual memory elements are characterized by including a material that reversibly changes its level of electrical conductance between at least first and second stable levels in response to an electrical stimulus being applied through the first and second conductive lines between which the memory element is connected.

6. The memory of claim 1, wherein the memory elements are sandwiched in the y-direction between the first and second conductive lines.

7. The memory of claim 6, wherein the memory elements are provided in continuous sheets of non-conductive material that individually extends past a plurality of crossings of the first and second conductive lines.

8. The memory of claim 6, wherein the memory elements include a metal oxide.

9. The memory of claim 8, wherein the metal oxide includes hafnium oxide.

10. The memory of claim 1, wherein the memory elements are positioned on one side of the second conductive lines in the z-direction.

11. The memory of claim 10, wherein the memory elements include at least one of a carbon material or a phase change material.

12. The memory of claim 1, wherein the individual memory elements are characterized by a level of electrical conductance that changes in response to an electrical stimulus applied thereto.

13. The memory of claim 1, wherein the memory elements are characterized by having at least first and second stable electrically detectable states that are selected by electrical stimuli applied thereto through the first and second conductive lines.

14. The memory of claim 13, additionally comprising a circuit connected to the first and second conductive lines to apply the electrical stimuli to selected ones of the memory elements, the electrical stimuli being applied to cause the selected memory elements to switch from their first to second stable states having substantially the same magnitude but different polarities as the electrical stimuli applied to cause the memory elements to switch from their second to first stable states.

15. The memory of any one of claims 1, 5, 6 and 10, wherein no diodes are connected in series with the memory elements between the first and second conductive lines.

16. The memory of claim 1, additionally comprising data input-output circuits connected to the third plurality of conductive lines.

17. The memory of claim 16, wherein the data input-output circuits include a plurality of sense amplifiers that are connected with the third conductive lines in a manner to provide a binary representation of data carried by the third conductive lines when data are being read from the memory.

18. The memory of claim 16, wherein the data input-output circuits additionally include data programming circuits that apply voltages to the third conductive lines for programming data into at least some of the memory elements connected thereto through the plurality of select devices.

19. A re-programmable non-volatile semiconductor memory, comprising:

a plurality of planes stacked on top of one another over a semiconductor substrate,

in individual ones of the planes, a plurality of control gate lines elongated in a x-direction and spaced apart in a y-direction across the plane,

a plurality of local bit lines extending from the substrate in a z-direction through the plurality of planes, arranged in a two-dimensional rectangular array in the x and y-directions and positioned through the individual planes between the control gate lines in the y-direction, the control gate and local bit lines therefore crossing adjacent each other at a plurality of locations in the plurality of planes,

wherein the x, y and z-directions are orthogonal with each other as three-dimensional rectangular coordinates,

a plurality of re-programmable non-volatile memory elements elongated in the z-direction through the plurality of planes and individually connected between the control gate and local bit lines adjacent the crossings thereof at the plurality of locations, individual memory elements having a detectable electrical characteristic that reversibly changes between at least two stable states in response to electrical stimuli applied thereto, and

a plurality of select devices formed in the substrate to individually connect selected ones of the plurality of local bit lines to selected ones of a plurality of global bit lines formed in the substrate.

20. The memory of claim 19, wherein the memory additionally comprises a control circuit formed in the substrate to connect, in response to control signals including addresses of some of the plurality of memory elements from which data are to be read, selected ones of the plurality of local bit lines to the plurality of global bit lines in a manner that only one of the local bit lines is connected to any one of the global bit lines at a time.

21. The memory of claim 19, wherein the memory additionally comprises a control circuit formed in the substrate to connect, in response to control signals including addresses of one or more groups of the plurality of memory elements to be reset, selected ones of the plurality of local bit lines to the plurality of global bit lines in a manner that at least two of the local bit lines are connected to any one of the global bit lines at a time

22. The memory of any one of claims 19, 20 and 21, wherein the plurality of global bit lines are elongated in the y-direction and spaced apart in the x-direction.

23. The memory of claim 19, wherein the memory elements are provided by layers of non-conductive material that individually extend continuously across multiple ones of the plurality of locations where the control gates and local bit lines cross adjacent each other.

24. The memory of claim 23, wherein the individual layers of non-conductive material extend continuously across multiple ones of the plurality of locations both across and within individual ones of the plurality of planes.

25. The memory of claim 23, wherein the individual layers of non-conductive material are sandwiched between the control gate lines and the local bit lines at individual ones of the plurality of locations where the control gate and local bit lines cross adjacent each other.

26. A method of operating a re-programmable non-volatile memory system, comprising:

utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having orthogonal x, y and z-directions and which comprises;

a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate,

a plurality of conductive local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array in the x and y-directions,

a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direetion between and separated from the plurality of local bit lines in the individual planes, wherein the local bit lines and word lines cross adjacent each other at a plurality of locations across the individual planes,

a plurality of re-programmable non-volatile memory elements elongated in the z-direction through the plurality of planes and individually connected between the local bit lines and the word lines adjacent the crossings thereof at the plurality of locations, the memory elements being individually switchable between at least first and second stable electrically detectable states such that application of a first electrical stimuli thereto causes the memory element to switch from the, first state to the second state and application of a second electrical stimuli thereto causes the memory element to switch from the second state to the first state, and

a plurality of select devices formed in the substrate that individually connect selected ones of the plurality of local bit lines to selected ones of a plurality of global bit lines in response to select control signals,

applying select control signals to the plurality of select devices in order to connect selected ones of the local bit lines to individual ones of the global bit lines, and

causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states by applying one of the first and second stimuli through the word lines and global bit lines between which the selected one or more of the plurality of memory elements are operably connected.

27. The method of claim 26, wherein applying select control signals includes applying the select control signals to the plurality of select devices in order to connect a row of the local bit lines extending in the x-direction to the global bit lines.

28. The method of claim 27, wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states includes simultaneously resetting to the first state two rows of memory elements connected to the selected row of local bit lines and along opposite sides thereof in the y-direction by applying the second electrical stimulus to a plurality of the global bit lines and to two of the word lines adjacent the selected row of local bit lines on said opposite sides thereof.

29. The method of claim 27, wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states additionally includes subsequently programming data into one of the two rows of reset memory elements by applying the first electrical stimulus to a plurality of the global bit lines and one of the word lines adjacent the selected row of local bit lines on the side thereof of the one row of memory elements being programmed.

30. The method of claim 27, additionally comprising reading the states of a row of memory elements along one side in the y-direction of the selected row of local bit lines by applying reading electrical stimuli to the global bit lines and word lines such that the states of the memory elements are read from an electrical quantity appearing on the global bit lines.

31. The method of claim 26, wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states additionally includes applying a plurality of pulses of the one of the first and second stimuli and, in between successive pulses, verifying the state of the one or more of the plurality of memory elements.

32. The method of claim 31, wherein verifying the state of the one or more of the plurality of memory elements includes use of a reference memory element that does not receive data programming.

33. The method of claim 26, wherein causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states includes use of a reference memory element that does not receive data programming.

34. The method of claim 26, wherein

utilizing at least one integrated circuit includes utilizing the plurality of re-programmable non-volatile memory elements that are individually switchable between more than two stable electrically detectable states by application of an electrical stimuli in addition to the first and second electrical stimuli, and

causing the selected one or more of the plurality of memory elements to simultaneously change between their individual more than two stable electrically detectable states includes applying the electrical stimuli in addition to the first and second electrical stimuli.

35. A method of forming a three-dimensional array of re-programmable non-volatile memory elements on a semi-conductor substrate, comprising:

forming switching circuits in the semi-conductor substrate,

thereafter forming a plurality of planes on top of each other and on top of the substrate, individual planes being formed by a dielectric layer with an electrically conductive layer thereover,

forming a plurality of parallel trenches through the dielectric and conductive layers of the plurality of planes and to the substrate in a single etch operation, wherein the conductive layers of the planes are separated into first electrically conductive lines extending between the trenches and with edges thereof making up portions of opposing sidewalls of the trenches,

forming layers of non-conductive re-programmable non-volatile memory material continuously along opposing sidewalls of the trenches including in contact with the edges of the first conductive lines, and

thereafter forming a plurality of second conductive lines within the trenches between and in contact with the opposing sidewall layers of memory material and spaced apart from each other along the trench, the second conductive lines additionally being formed to extend away from contact with the switching circuits in the substrate and continuously through the plurality of planes,

wherein the three-dimensional array of re-programmable non-volatile memory elements is formed in portions of the layers of the memory material positioned between the edges of the first conductive lines and the second conductive lines.

36. The method of claim 35, wherein forming layers of memory, material comprises forming layers of memory material that includes a metal oxide.

37. The method of claim 36, wherein the metal oxide used in forming the layers of memory material includes hafnium oxide.

38. The method of claim 35, wherein forming the plurality of planes and trenches comprises:

forming a first plurality of the planes on top of each other and on top of the substrate,

forming a first plurality of the parallel trenches through the dielectric and conductive layers of the first plurality of planes and to the substrate in a first continuous etch operation,

thereafter forming a second plurality of the planes on top of each other and on top of the first plurality of planes, and

forming a second plurality of parallel trenches through the dielectric and conductive layers of the second plurality of planes and through to the first plurality of planes in alignment with the first plurality of trenches in a second continuous etch operation.

39. A method of forming a three-dimensional array of re-programmable non-volatile memory elements on a semi-conductor substrate, comprising:

forming switching circuits in the semi-conductor substrate,

forming a stack of a plurality of planes on top of the semiconductor substrate, the planes being individually formed in sequence by a method comprising;

forming a first dielectric as a continuous bottom layer,

forming a plurality of re-programmable non-volatile memory elements in a two-dimensional array across the dielectric layer, the array having rows and columns of discrete memory elements extending in respective first and second directions that are orthogonal with each other, and

forming a first plurality of conductive lines having lengths extending in the first direction and being spaced apart in the second direction to overlay and form electrical contact with rows of memory elements, and

after forming the stack of the plurality of planes, forming a second plurality of conductive lines that contact the switching circuits in the substrate and extend up through the plurality of planes, the second conductive lines being positioned between adjacent memory elements in the second direction in a manner to have an electrical connection therewith but remain insulated from the first conductive lines,

wherein the three-dimensional array of re-programmable non-volatile memory elements is formed by the two-dimensional arrays of memory elements in the stack of the plurality of planes that are individually electrically connected between one of the first conductive lines and one of the second conductive lines.

40. The method of claim 39, wherein forming the second plurality of conductive lines includes forming the second plurality of conductive lines in contact with adjacent memory elements in the second direction.

41. The method of claim 39, wherein

formation of the individual planes additionally comprises forming a plurality of bottom electrodes on the bottom dielectric layer which extend in the second direction, and thereafter forming the plurality of memory elements on portions of the bottom electrodes, and

forming the second plurality of conductive lines includes forming the second plurality of conductive lines in contact with the plurality of bottom electrodes, whereby the electrical connection between individual ones of the plurality of memory elements and the plurality of second conductive lines is made through one of the plurality of bottom electrodes.