Phase change memory apparatus

• US 7,983,077 B2
• Filed: 06/30/2009
• Issued: 07/19/2011
• Est. Priority Date: 05/15/2009
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Park, Kyoung Wook
• Primary Examiner(s): Le; Vu A
• Assistant Examiner(s): Yang; Han
• Application Number:
  US12/494,587
• Publication Number:
  US 20100290275A1
• Time in Patent Office: 749 Days
• Field of Search: 365/163, 365/148, 365/210.1, 365/210.15
• US Class Current: 365/163
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods

Abstract

A phase change memory apparatus is presented. The phase change memory apparatus includes a phase change memory cell, a sense amplifier, and a voltage selecting unit. The sense amplifier is configured to differentially amplify a current that through the memory cell and a comparison voltage. The voltage selecting unit is configured to provide a reference voltage as the comparison voltage when performing a normal read function and to selectively provide either a first voltage level or a second voltage level as the comparison voltage in accordance with data when performing a verify read function.

Claims

1. A phase change memory apparatus comprising the memory cell such that the apparatus is configured to perform a write verify function in the memory cell, wherein the phase change memory apparatus is configured to write a first state level data or a second state level data in the memory cell such that when the first state level data is written, then the apparatus is configured to perform a verify read function with a first voltage level, and when the second state level data is written, then the apparatus is configured to perform the verify read function with a second voltage level which has a different voltage level from the first voltage level.

2. The phase change memory apparatus according to claim 1, wherein the first voltage level is higher than a reference voltage and the second voltage level is lower than the reference voltage.

3. The phase change memory apparatus according to claim 2, wherein the apparatus is configured to perform a normal read function using the reference voltage.

4. A phase change memory apparatus comprising:

a phase change memory cell;

a sense amplifier configured to differentially amplify a current that through the memory cell and a comparison voltage; and

a voltage selecting unit configured to provide a reference voltage as the comparison voltage when performing a normal read function and to selectively provide either a first voltage level or a second voltage level which has a different voltage level from the first voltage level as the comparison voltage in accordance with data when performing a verify read function.

5. The phase change memory apparatus according to claim 4, wherein the first voltage level is higher than the reference voltage and the second voltage level is lower than the reference voltage.

6. The phase change memory apparatus according to claim 5, wherein the voltage selecting unit comprises:

a verify read controller configured to generate a first control signal in response to a verify read signal and the data;

a normal read controller configured to generate a second control signal in response to the verify read signal and the normal read signal; and

an output unit configured to output anyone of the first voltage level, the second voltage level, and the reference voltage as the comparison voltage in response to the first and second control signals.

7. The phase change memory apparatus according to claim 6, wherein when the verify read signal is enabled, then the verify read controller disables the first control signal if the data is at a first state level and enables the first control signal if the data is a second state level.

8. The phase change memory apparatus according to claim 7, wherein the output unit is configured to provide the second voltage level as the comparison voltage when the first control signal is enabled and to provide the first voltage level as the comparison voltage when the first control signal is disabled.

9. The phase change memory apparatus according to claim 6, wherein the normal read controller disables the second control signal when the verify read signal is enabled, and the normal read controller enables the second control signal when the verify read signal is disabled when the normal read signal is enabled.

10. The phase change memory apparatus according to claim 9, wherein the output unit provides the reference voltage as the comparison voltage when the second control signal is enabled.