Non-volatile memory apparatus and method with deep N-well

• US 7,983,081 B2
• Filed: 12/14/2008
• Issued: 07/19/2011
• Est. Priority Date: 12/14/2008
• Status: Active Grant

• Current Assignee: Chipmos Technologies Incorporated (Chipmos)
• Original Assignee: Chipmos Technologies Incorporated (Chipmos)
• Inventors: Fang, Gang-Feng, Leung, Wingyu
• Primary Examiner(s): Mai; Son L
• Application Number:
  US12/334,510
• Publication Number:
  US 20100149874A1
• Time in Patent Office: 947 Days
• Field of Search: 365/185.08
• US Class Current: 365/185.08
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

An apparatus and method of an electrically programmable and erasable non-volatile memory cell with a deep N-well to isolate the memory cell from the substrate is disclosed. In one embodiment, a non-volatile memory apparatus includes at least one non-volatile memory cell fabricated on a P substrate, with a deep N-well located in the P substrate, while a P-well and an N-well are located in the deep N-well. The memory cell further includes a PMOS transistor located in the N-well, in which the PMOS transistor includes a PMOS gate-oxide, and an NMOS capacitor located in the P-well. The NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide. The memory cell further includes a floating gate comprised of a poly-silicon gate overlying the PMOS transistor and the NMOS capacitor.

Claims

1. A non-volatile memory apparatus comprised of at least one non-volatile memory cell fabricated on a P substrate, wherein each non-volatile memory cell comprises:

a deep N-well located in the P substrate, wherein a P-well and an N-well are located in the deep N-well;

a PMOS transistor located in the N-well, wherein the PMOS transistor includes a PMOS gate-oxide;

an NMOS capacitor located in the P-well, wherein the NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide; and

a floating gate comprised of a poly-silicon gate overlying the PMOS transistor and the NMOS capacitor.

2. The non-volatile memory apparatus of claim 1, wherein the non-volatile memory system is configured to add negative charge to the floating gate using channel hot electron tunneling.

3. The non-volatile memory apparatus of claim 2, wherein the non-volatile memory system is configured to remove negative charge from the floating gate using Fowler-Nordheim tunneling.

4. The non-volatile memory apparatus of claim 1, wherein the non-volatile memory system is configured to be formed using a single-poly process.

5. The non-volatile memory apparatus of claim 1, further comprising a control gate, wherein the control gate is comprised of a channel region of the NMOS capacitor.

6. The non-volatile memory apparatus of claim 1, further comprising a tunnel oxide located in the PMOS gate-oxide overlying a channel area of the PMOS transistor, wherein the tunnel oxide is configured to allow electrons to tunnel between the floating gate and a PMOS channel during program and erase operations.

7. The non-volatile memory apparatus of claim 1, wherein the NMOS capacitance is larger than a PMOS gate capacitance.

8. The non-volatile memory apparatus of claim 1, wherein the memory cell further comprises a second PMOS transistor located in the N-well.

9. The non-volatile memory apparatus of claim 8, wherein a drain of the PMOS transistor is coupled to a source of the second PMOS transistor.

10. The non-volatile memory apparatus of claim 8, wherein the second PMOS transistor is configured to minimize a program disturbance or read disturbance of the memory system.

11. The non-volatile memory apparatus of claim 1, wherein the non-volatile cells are arranged in a plurality of rows and columns, wherein

the NMOS capacitors of the memory cells are located in a merged P-well,

the PMOS transistors of the memory cells are located in a merged N-well, and

the memory cells are located in a merged deep N-well.

12. The non-volatile memory system of claim 11, further comprising:

a bit line connected to a drain of each PMOS transistor of a column of non-volatile memory cells,

a common line connected a source of each PMOS transistor of a column of non-volatile memory cells,

a word line connected to the N+ coupling region of each NMOS capacitor of a row of non-volatile memory cells.

13. The non-volatile memory system of claim 12, wherein each of the non-volatile memory cells of the array is configured to be independently programmed and erased.

14. The non-volatile memory system of claim 9, wherein the non-volatile cells are arranged a plurality of rows and columns, wherein

NMOS capacitors of the memory cells are located in a P-well;

PMOS transistors of the memory cells are located in an N-well; and

the memory cells are located in a deep N-well.

15. The non-volatile memory system of claim 14, wherein each of the non-volatile memory cells of the array is configured to be independently programmed and erased.

16. A method of fabricating a non-volatile memory apparatus including at least one non-volatile memory cell on a P substrate, wherein the method of forming each non-volatile memory cell comprises:

forming a deep N-well in the P substrate, wherein a P-well and an N-well are located in the deep N-well;

placing a PMOS transistor in the N-well, wherein the PMOS transistor includes a PMOS gate-oxide;

forming an NMOS capacitor in the P-well, wherein the NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide; and

placing a floating gate comprised of a poly-silicon over the channel region of the PMOS transistor and the NMOS capacitor.

17. The method of claim 16, further comprising configuring the non-volatile memory apparatus to add negative charge to the floating gate using channel hot electron tunneling.

18. A method, comprising:

adding negative charge to a floating gate of a non-volatile memory cell using channel hot electron tunneling, wherein the memory cell is fabricated on a P substrate and comprises a deep N-well located in the P substrate, wherein a P-well and an N-well are located in the deep N-well, a PMOS transistor located in the N-well, wherein the PMOS transistor includes a PMOS gate-oxide, an NMOS capacitor located in the P-well, wherein the NMOS capacitor includes an N+ coupling region located in the P-well, and an NMOS gate-oxide, and a floating gate comprised of a poly-silicon gate overlying the PMOS transistor and the NMOS capacitor; and

removing negative charge from the floating gate using Fowler-Nordheim tunneling.

19. The method of claim 18, wherein the tunneling oxide for both adding and removing negative charge from the floating gate of the non-volatile memory cell is the gate oxide over the PMOS channel region.

20. The method of claim 19, further comprising isolating the PMOS transistor using an additional PMOS transistor to minimize a program disturb problem, wherein the additional PMOS transistor is located next to the first PMOS transistor.