Dual function compatible non-volatile memory device

• US 7,983,099 B2
• Filed: 10/24/2008
• Issued: 07/19/2011
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Lam; David
• Application Number:
  US12/258,056
• Publication Number:
  US 20090161451A1
• Time in Patent Office: 998 Days
• Field of Search: 365/191, 365/226, 365/233.1, 365/233.5, 365/230.01, 711/167, 711/105
• US Class Current: 365/191
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Claims

1. A memory device configurable to operate in a first mode and a second mode, comprising:

ports for receiving one of a first function assignment corresponding to the first mode and a second function assignment corresponding to the second mode;

an interface and control circuit for receiving a command from at least one of the ports, and configurable for decoding the command in one of the first mode and the second mode, the command being decoded for controlling core circuits of the memory device; and

a mode detector connected to a selected port of the ports for configuring the interface and control circuit to decode the command in the first mode when the voltage supply is detected, and to decode the command in the second mode when the voltage supply is undetected.

2. The memory device of claim 1, wherein the interface and control circuit includes

synchronous circuits coupled to the ports for receiving the command and generating decoded synchronous command signals when the voltage supply is undetected by the mode detector;

asynchronous circuits coupled to the ports for receiving the command and generating decoded asynchronous command signals when the voltage supply is detected by the mode detector;

control logic for generating identical internal control signals in response to the decoded synchronous command signals and the decoded asynchronous command signals; and

,

a selector for selectively passing one of the decoded synchronous command signals and the decoded asynchronous command signals to the control logic in response to a detected state of the voltage supply.

3. The memory device of claim 2, wherein the mode detector includes

a voltage detector for providing a status signal when the voltage supply has reached a predetermined level, and

mode logic coupled to the selected port for driving a mode signal from a first logic level to a second logic level in response to the status signal while the selected port is biased to a voltage level other than the voltage supply.

4. The memory device of claim 3, wherein the synchronous circuits includes synchronous buffers coupled to each of the ports and a synchronous command decoder, and the asynchronous circuits includes asynchronous buffers coupled to each of the ports and an asynchronous command decoder.

5. The memory device of claim 4, wherein each port in the first function assignment and the second function assignment of a same type have common buffers functioning as both the synchronous buffers and the asynchronous buffers, where the type can be one of an input type and an output type.

6. The memory device of claim 5, wherein the interface and control circuit further includes signal path switches for selectively coupling each of the ports to the synchronous command decoder through the synchronous buffers in response to the first logic level of the mode signal, and for selectively coupling each of the ports to the asynchronous command decoder through the asynchronous buffers in response to the second logic level of the mode signal.

7. The memory device of claim 6, wherein the interface and control circuit further includes

first power switches for decoupling the voltage supply from the synchronous circuits in response to the second logic level of the mode signal, and

second power switches for decoupling the voltage supply from the asynchronous circuits in response to the first logic level of the mode signal.

8. The memory device of claim 1, wherein the mode logic includes a latch for maintaining the second logic level of the mode signal in response to the status signal.

9. The memory device of claim 1, wherein the selected port is a functional port used during normal operation of one of the first mode and the second mode.

10. The memory device of claim 1, wherein the selected port is a dedicated port unused during normal operation of both the first mode and the second mode.