Integrated computer array with independent functional configurations

• US 7,984,266 B2
• Filed: 06/05/2007
• Issued: 07/19/2011
• Est. Priority Date: 03/16/2004
• Status: Active Grant

• Current Assignee: Array Portfolio LLC
• Original Assignee: VNS Portfolio LLC
• Inventors: Moore, Charles H.
• Primary Examiner(s): Chan; Eddie
• Assistant Examiner(s): FAHERTY, COREY S
• Application Number:
  US11/810,183
• Publication Number:
  US 20070245121A1
• Time in Patent Office: 1,505 Days
• Field of Search: 712/10
• US Class Current: 712/10
• CPC Class Codes: G06F 9/5044 considering hardware capabilities
• CPC Class Codes: G06F 9/5066 Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs mappping at compile time, see G06F8/451

Abstract

A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 25 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output.

Claims

1. A computer array, comprising:

a plurality of independently functioning computers arranged in a matrix, wherein each of said plurality of computers is substantially similar in at least one of structure, circuitry, layout, and operational characteristics, and wherein each of said plurality of computers has at least two nearest neighbor computers;

a plurality of sets of interconnecting data lines, wherein each individual set of said plurality of sets is disposed between and exclusively used by an individual computer and one of its nearest neighbor computers of said plurality of computers or disposed between and exclusively used by said individual computer and an external device;

a plurality of functional configurations each associated with at least some of said plurality of computers, wherein some of said plurality of functional configurations differ from others of said plurality of functional configurations; and

executable code defining a plurality of assigned tasks, wherein each of said plurality of tasks is executed by at least one of said plurality of computers according to said plurality of functional configurations associated with each of said plurality of computers, wherein some of said plurality of tasks differ from others of said plurality of tasks;

thereby enabling execution of said plurality of tasks by said plurality of computers associated with said plurality of functional configurations; and

wherein

the execution of some of said tasks differ from the execution of others of said tasks;

said array is positioned on a single integrated circuit substrate;

intercommunication between one of said plurality of computers and one of its nearest neighbor computers is carried out through the processors of said one of said plurality of computers and said one of its nearest neighbor computers;

intercommunication between said one of said plurality of computers and a non-nearest neighbor computer must be carried out through the processors of said one of said plurality of computers and said one of its nearest neighbor computers; and

each of said plurality of independently functioning computers includes read-only memory for storing instructions, random access memory for storing data and instructions, and a processor for executing the instructions.

2. The computer array of claim 1, wherein some of said plurality of computers function internally in an asynchronous manner.

3. The computer array of claim 1, wherein some of said plurality of sets of interconnecting data lines comprise asynchronous parallel data lines.

4. The computer array of claim 1, wherein said array comprises a homogeneous array.

5. The computer array of claim 1, wherein some of said plurality of computers comprise a computational group of computers and others of said plurality of computers comprise an input/output group of computers.

6. The computer array of claim 1, wherein said array comprises a plurality of two by two computer arrays, each of said two by two computer arrays being directly adjacent to a mirror image computer array of itself.

7. The computer array of claim 1, wherein:

the computers operate internally in an asynchronous manner; and

the computers communicate with each other asynchronously via the interconnecting data lines.

8. The computer array of claim 1, wherein:

at least one of the read-only memory and the random-access memory in each of the computers is dedicated memory.

9. The computer array of claim 1, wherein:

the plurality of independently functioning computers includes at least twenty-four independently functioning computers.

10. The computer array of claim 9, wherein:

at least some of the computers are physically arrayed in a 4 by 6 matrix.

11. The computer array of claim 9, wherein:

at least some of the computers are physically arrayed in a 5 by 5 matrix.

12. The computer array of claim 1, wherein:

data communicated within the matrix from a first one of the computers to a second one of the computers must necessarily pass through at least one of the other computers.

13. The computer array of claim 10, wherein:

data communicated within the matrix from the first one of the computers to the second one of the computers must necessarily pass through at least two of the other computers.

14. The computer array of claim 1, wherein:

at least one of said plurality of computers includes additional circuitry specific to one of said plurality of functional configurations associated with said at least one of said plurality of computers.

15. The computer array of claim 1, wherein:

each of said plurality of assigned tasks accomplishes at least a portion of the function of a subcomponent of a consumer device.

16. A method of making a computer array, comprising:

arranging a plurality of independently functioning computers in a matrix, wherein each of said plurality of computers is substantially similar in at least one of structure, circuitry, layout, and operational characteristics, and wherein each of said plurality of computers has at least two nearest neighbor computers;

forming a plurality of sets of interconnecting data lines, wherein each individual set of said plurality of sets is disposed between and exclusively used by an individual computer and one of its nearest neighbor computers of said plurality of computers or is disposed between and exclusively used by said individual computer and an external device;

forming a plurality of functional configurations each associated with at least some of said plurality of computers, wherein some of said plurality of functional configurations differ from others of said plurality of functional configurations;

assigning a plurality of tasks to said plurality of computers, wherein each task of said plurality of tasks is assigned to at least one computer of said plurality of computers according to said functional configurations assigned to said plurality of computers, wherein some of said plurality of tasks differ from others of said plurality of tasks; and

wherein

said array is positioned on a single integrated circuit substrate;

said interconnecting data lines are formed such that intercommunication between one of said plurality of computers and one of its nearest neighbor computers is carried out through the processors of said one of said plurality of computers and said one of its nearest neighbor computers;

said interconnecting data lines are formed such that intercommunication between said one of said plurality of computers and a non-nearest neighbor computer must be carried out through the processors of said one of said plurality of computers and said one of its nearest neighbor computers; and

each of said plurality of independently functioning computers includes read-only memory for storing instructions, random access memory for storing data and instructions, and a processor for executing the instructions.

17. The method of claim 16, wherein some of said plurality of computers function internally in an asynchronous manner.

18. The method of claim 16, wherein some of said plurality of sets of interconnecting data lines comprise asynchronous parallel data lines.

19. The method of claim 16, wherein said array comprises a homogeneous array.

20. The method of claim 16, wherein some of said plurality of computers comprise a computational group of computers and others of said plurality of computers comprise an input/output group of computers.

21. The method of claim 16, wherein said array comprises a plurality of two by two computer arrays, each of said two by two computer arrays being directly adjacent to a mirror image computer array of itself.

22. The method of claim 16, wherein:

the computers operate internally in an asynchronous manner; and

the computers communicate with each other asynchronously via the interconnecting data lines.

23. The method of claim 16, wherein:

at least one of the read-only memory and the random-access memory in each of the computers is dedicated memory.

24. The method of claim 16, wherein:

the step of arranging a plurality of independently functioning computers in a matrix includes arranging at least twenty-four independently functioning computers in a matrix.

25. The method of claim 24, wherein:

at least some of the computers are physically arrayed in a 4 by 6 matrix.

26. The method of claim 24, wherein:

at least some of the computers are physically arrayed in a 5 by 5 matrix.

27. The method of claim 16, wherein:

the step of forming a plurality of sets of interconnecting data lines includes forming the sets of interconnecting data lines such that data communicated within the matrix from a first one of the computers to a second one of the computers must necessarily pass through at least one of the other computers.

28. The method of claim 27, wherein:

data communicated within the matrix from the first one of the computers to the second one of the computers must necessarily pass through at least two of the other computers.

29. The method of claim 16, wherein:

said step of forming said plurality of functional configurations includes forming additional circuitry specific to one of said plurality of functional configurations, said additional circuitry associated with at least one of said plurality of computers.

30. The method of claim 16, wherein:

each of said plurality of assigned tasks accomplishes at least a portion of the function of a subcomponent of a consumer device.