System and method for providing DRAM device-level repair via address remappings external to the device

• US 7,984,329 B2
• Filed: 09/04/2007
• Issued: 07/19/2011
• Est. Priority Date: 09/04/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Dreibelbis, Jeffrey H., Tremaine, Robert B., Lastras-Montano, Luis A., Anand, Darren L., Kilmer, Charles A., Maule, Warren E.
• Primary Examiner(s): Iqbal; Nadeem
• Application Number:
  US11/849,452
• Publication Number:
  US 20090063896A1
• Time in Patent Office: 1,414 Days
• Field of Search: 714 2- 8, 714 13- 16, 714/18, 714/20, 714/21, 714/30, 714/31, 714/37, 714/39, 714/42, 714/54, 714/25
• US Class Current: 714/6.13
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line.

Claims

1. A memory controller in a system, the memory controller comprising:

one or more memory modules comprising one or more memory devices, each of the one or more memory devices including addressable redundant and non-redundant memory blocks; and

a mechanism for utilizing one or more redundant memory blocks in a memory device in place of one or more failing non-redundant memory blocks in the memory device via an address remapping external to the memory device, the memory device one of the one or more memory devices, and the remapping occurring while the system is on-line.

2. The memory controller of claim 1 wherein the mechanism determines if the remapping improves reliability of the memory system and backs out the remapping if it is determined that the reliability has not improved.

3. The memory controller of claim 1 wherein the mechanism accesses data at the one or more redundant memory blocks in response to requests to access data at the one or more failing non-redundant memory blocks.

4. The memory controller of claim 3 wherein the mechanism augments a memory device access protocol to include the information that a redundant memory block will be utilized.

5. The memory controller of claim 3 wherein the mechanism utilizes an additional address pin to communicate to the memory devices that a redundant memory block will be accessed.

6. The memory controller of claim 3 wherein the mechanism utilizes a change mode command to communicate to the memory devices that a redundant memory block will be accessed.

7. The memory controller of claim 3 wherein the mechanism utilizes a command to initiate a configuration mode in the memory device, wherein the configuration mode allows access to the redundant memory blocks.

8. The memory controller of claim 1 wherein the redundant and non-redundant memory blocks include one or more of a block of rows, a block of columns, and a subset of one or more rows and one or more columns.

21. The memory controller of claim 1 wherein the memory device is a dynamic random access memory (DRAM).

9. A hub device in a memory system, the hub device comprising:

one or more memory devices, each of the one or more memory devices including addressable redundant and non-redundant memory blocks; and

a mechanism for utilizing one or more redundant memory blocks in a memory device in place of one or more failing non-redundant memory blocks in the memory device via a remapping external to the memory device, the memory device one of the one or more memory devices, and the remapping occurring while the system is on-line.

10. The hub device of claim 9 wherein the mechanism determines if the remapping improves reliability of the memory system and backs out the remapping if it is determined that the reliability has not improved.

11. The hub device of claim 9 wherein the mechanism accesses data at the one or more redundant memory blocks in response to requests to access data at the one or more failing non-redundant memory blocks.

12. The hub device of claim 11 wherein the mechanism augments a memory device access protocol to include the information that a redundant memory block will be utilized.

13. The hub device of claim 11 wherein the mechanism utilizes an additional address pin to communicate to the memory devices that a redundant memory block will be accessed.

14. The hub device of claim 11 wherein the mechanism utilizes a change mode command to communicate to the memory devices that a redundant memory block will be accessed.

15. The hub device of claim 11 wherein the mechanism utilizes a command to initiate a configuration mode in the memory device, wherein the configuration mode allows access to the redundant memory blocks.

16. The hub device of claim 9 wherein the addressable non-redundant and redundant memory blocks include one or more of a block of rows, a block of columns, and a subset of one or more rows and one or more columns.

22. The hub device of claim 9 wherein the memory device is a dynamic random access memory (DRAM).

17. A computer implemented method for providing DRAM device level repair in a memory system, the method comprising:

receiving a request to remap data in a non-redundant memory block of a memory device into a redundant location on the same memory device, the redundant location having a redundant location address;

copying the data from the non-redundant memory block of the memory device into the redundant location of the same memory device and correlating the non-redundant memory block address to the redundant location address;

monitoring the memory system to determine if reliability has improved while continuing to update the data in both the non-redundant memory block of the memory device and the redundant location of the same memory device in response to requests to access the data at the redundant memory block; and

copying the data from the redundant location back into the non-redundant memory block and removing the correlation between the non-redundant memory block address and the redundant location address, in response to determining that the reliability has not improved.

18. The method of claim 17 wherein the method is executed by a memory controller in communication with the memory device or by a hub device in communication with the memory device.

19. A computer implemented method for providing DRAM device level repair in a memory system, the method comprising:

receiving a request to access data at an address in a non-redundant memory block of a memory device, the memory device including non-redundant and redundant memory blocks;

determining, responsive to receiving the request to access data if the address requires remapping; and

in response to determining that the address requires remapping;

remapping the address into a redundant location address on the same memory device;

copying the data from the non-redundant memory block to the redundant memory block; and

accessing the data at the redundant location address in the same memory device in response to the request, thereby providing memory device level repair while the system is on-line via an address remapping between two memory locations on the same memory device via a memory remapping external to the memory device.

20. The method of claim 19 wherein the method is executed by a memory controller in communication with the memory device or by a hub device in communication with the memory device.