Series equivalent scans across multiple scan topologies

• US 7,984,348 B2
• Filed: 07/29/2009
• Issued: 07/19/2011
• Est. Priority Date: 07/29/2008
• Status: Expired

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Primary Examiner(s): Ton; David
• Application Number:
  US12/511,983
• Publication Number:
  US 20100031100A1
• Time in Patent Office: 720 Days
• Field of Search: 702/150, 370/352, 714/726, 714/731, 714/733, 714/727, 714/729
• US Class Current: 714/727
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

Performing series equivalent scans spanning a plurality of scan technologies in a complex scan topology may be performed by performing shift operations in the complex scan topology while only one branch of the complex scan topology connectivity is enabled, and performing capture and update operations in parallel while scan topology connectivity of two or more of the plurality of scan technologies is enabled.

Claims

1. A method for performing series equivalent scans in a target system comprising a complex scan topology with a plurality of branches, the method comprising:

performing shift operations in the complex scan topology while scan path connectivity of only one branch of the complex scan topology is enabled, wherein a first branch and a second branch are different test access port technologies, and wherein a first protocol is used to perform shift operations on the first branch and a different second protocol is used to perform shift operations on the second branch; and

performing capture and update operations in the first branch and the second branch of the complex scan topology in parallel.

2. The method of claim 1, wherein test access ports of at least two of the branches are connected in parallel.

3. The method of claim 1, wherein while the first branch is selected to perform a shift operation, the second branch is deselected and remains dormant.

4. The method of claim 3, wherein a deselected branch ignores protocol signaling except for the detection of reset events, and selection events and the selection sequence that follows selection events.

5. The method of claim 4, wherein a deselected branch responds to a selection escape and the selection sequence that follows it to be selected.

6. The method of claim 3, wherein selection and deselection provides for the selection of a specific technology, or group of technologies of a complex scan topology by selecting a series, a Star-4, a Star-2, and all of the Series, Star-4 and Star-2 topologies.

7. The method of claim 3, wherein selecting a hierarchy level below a debug test system (DTS) coupled to the target system comprises selection of an Adapter Test Access Port Controller (ADTAPC) from among a plurality of ADTAPCs within a complex scan topology.

8. The method of claim 3, wherein selection of the hierarchy level below the ADTAPC comprises selecting a Chip Level Test Access Port Controller (CLTAPC) from among a plurality of CLTAPCs, each connected to an Adapter Test Access Port Controller (ADTAPC).

9. The method of claim 3, wherein selection of the hierarchy level below the CLTAPC comprises selecting an Embedded Level Test Access Port Controller (EMTAPC) connected to a Chip Level Test Access Port Controller (CLTAPC).

10. The method of claim 1, wherein performing capture and update operations in parallel comprises receiving a select-all command by the first and second branches, followed by receiving information that causes a TAPC state progression to a Capture_xR state via the Update-xR state through one or more states of a test access port controller (TAPC) in each of the first branch and second branch.

11. The method of claim 10, wherein performing shift operations comprises receiving a sequence of selection events and selection sequences by the plurality of branches to sequentially select a respective branch, followed by TAPC state progressions that include the Shift-xR state, with this TAPC state progression followed by one or more chip level test access ports (CLTAPCs) in the selected branch.

12. A digital system, comprising:

a plurality of components, each having a test access port (TAP) configured to perform diagnostic tests on the associated component in response to commands presented to the TAPs, the TAPs of the plurality of components connected to form a complex scan topology having two or more branches, the complex scan topology configured to couple to the source of commands;

wherein a first branch and a second branch have different test access port technologies, and wherein the first branch is configured to respond to a first protocol to perform shift operations while the second branch is in an offline mode, and the second branch is configured to respond to a different second protocol to perform shift operations while the first branch is in an offline mode; and

wherein the first branch and the second branch are configured to respond to a common protocol to perform capture and update operations in parallel.

13. The digital system of claim 12, wherein each TAP of the plurality of components comprises:

a test clock (TCK) input and a test mode select (TMS) input configured to receive test signals from a source of commands

a TAP scan path having one or more bits, the TAP scan path connected to a test data input (TDI) and a test data output (TDO), wherein the TDI and TDO are configured to be coupled to a scan path of the complex scan topology;

a topology register, programmable when the TAP can be deployed in multiple scan topologies and hardwired to a value when the TAP can be deployed in a single scan topology, coupled to control logic, wherein the topology register records the topology type in which the TAPC is deployed, selectable as part of a Series Scan Topology when the Topology Register indicates the TAP.7 controller is deployed in a Series Scan Topology, selectable as part of a Series Scan Topology when the Topology Register indicates the TAP.7 controller is deployed in a Series Scan Topology, selectable as part of a Star2-Scan Topology when the Topology Register indicates the TAP.7 controller is deployed in a Star-2 Scan Topology, Selectable independent of the Topology Register value when the selection criteria specifies any TAP.7 Scan topology Series, Star-4, and Star-2) and

the control logic coupled to the TCK(C) and TMS(C) inputs and configured to detect a selection event and an selection criteria received on the TMS(C) input, and further configured to place the TAP controller (the ADTAPC) in an online mode when the selection criteria matches a topology type identified by the Topology Register value.

14. The digital system of claim 13, wherein the selection event and the selection criteria are received together serially.

15. The digital system of claim 13, wherein the control logic is further configured to receive and detect a sequence of bit values prior to receiving the selection event which determine whether the selection event initiates a selection sequence.

16. The digital system of claim 13, wherein the control logic is further configured to place the TAP controller in an offline mode when the selection criteria does not match the activation criteria.

17. The digital system of claim 13, wherein the selection event specifies a specific technology of a complex scan topology by selecting a series, a Star-4, a Star-2, all of the series, Star-4 and Star-2 topologies, or another technology.