System and method for random defect yield simulation of chip with built-in redundancy

• US 7,984,399 B1
• Filed: 12/27/2007
• Issued: 07/19/2011
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Fales, Jonathan, Koshy, Mathew, Ruehl, Roland, Gumaste, Udayan
• Primary Examiner(s): Doan; Nghia M
• Application Number:
  US11/965,681
• Time in Patent Office: 1,300 Days
• Field of Search: 716 4- 5, 716104-107, 716111-112, 702127-129, 702179-181, 714703-705
• US Class Current: 716/106
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip'"'"'s architecture.

Claims

1. A method comprising:

providing a simulation model to determine a random yield for a layout design, wherein the layout design includes a memory array with one or more redundant rows or columns, wherein the simulation model comprises a failure model for the memory array;

determining a probability of failure of the memory array of the layout design, wherein the probability of failure of the memory array comprises accumulating a probability of failure of a two-dimensional array of bits, a probability of failure of a column of replaceable row elements and a probability of failure of a row of replaceable column elements through a sum of products of probabilities of fail and probabilities of no fail; and

calculating, by using a processor, the random yield for the layout design based at least in part upon the accumulated probabilities of failure.

2. The method of claim 1, wherein the failure model comprises at least one of a failure model for a periphery of the memory array, a failure model for the array elements of the memory array, a failure model for the replaceable row elements, or a failure model for the replaceable column elements.

3. The method of claim 2, wherein a the failure model for the row elements is given by a probability function comprising:

4. The method of claim 1, wherein a probability of failure for a subarray model is determined with the simulation model comprising:

P_SA=P_BSAP_RREP_RCE+P_RRE(1−

P_BSA)+P_RCE(1−

P_RRE)+P_BSA(1−

P_RCE)

Wherein the P_SA represents the probability of failure for the subarray model, the P_BSA represents the probability of failure of the two-dimensional array of bits, the P_RRE represents the probability of failure of the column of the replaceable row elements and the P_RCE represents the probability of failure of the row of replaceable the column elements.

5. The method of claim 1, wherein the random yield comprises a random defect yield.

6. The method of claim 1, wherein the layout design includes an electronic design.

7. An apparatus comprising:

a processor programmed for;

providing a simulation model to determine a random yield for a layout design, wherein the layout design includes a memory array with redundant row or column, wherein the simulation model comprises a failure model for the memory array;

determining a probability of failure of the memory array of the layout design, wherein the probability of failure of the memory array comprises accumulating a probability of failure of a two-dimensional array of bits, a probability of failure of a column of replaceable row elements and a probability of failure of a row of replaceable column elements through a sum of products of probabilities of fail and probabilities of no fail; and

calculating the random yield for the layout design based at least in part upon the accumulated probabilities of failure.

8. The apparatus of claim 7, wherein the failure model comprises at least one of a failure model for a periphery of the memory array, a failure model for the array elements of the memory array, a failure model for the replaceable row elements, or a failure model for the replaceable column elements.

9. The apparatus of claim 7, wherein the random yield comprises a random defect yield.

10. The apparatus of claim 7, wherein the layout design includes an electronic design.

11. The apparatus of claim 7, wherein a probability of failure for a subarray model is determined with the simulation model comprising:

P_SA=P_BSAP_RREP_RCE+P_RRE(1−

P_BSA)+P_RCE(1−

P_RRE)+P_BSA(1−

P_RCE)

Wherein the P_SA represents the probability of failure for the subarray model, the P_BSA represents the probability of failure of the two-dimensional array of bits, the P_RRE represents the probability of failure of the column of the replaceable row elements and the P_RCE represents the probability of failure of the row of replaceable the column elements.

12. A computer program product comprising a volatile or non-volatile computer-user medium having a set of stored instructions, an execution of which by a processor causes a process to be performed, the process comprising:

providing a simulation model to determine a random yield for a layout design, wherein the layout design includes a memory array with redundant row or column, wherein the simulation model comprises a failure model for the memory array;

determining a probability of failure of the memory array of the layout design, wherein the probability of failure of the memory array comprises accumulating a probability of failure of a two-dimensional array of bits, a probability of failure of a column of replaceable row elements and a probability of failure of a row of replaceable column elements through a sum of products of probabilities of fail and probabilities of no fail; and

calculating, by one or more processors, the random yield for the layout design based at least in part upon the accumulated probabilities of failure.

13. The product of claim 12, wherein the failure model comprises at least one of a failure model for a periphery of the memory array, a failure model for the array elements of the memory array, a failure model for the replaceable row elements, or a failure model for the replaceable column elements.

14. The product of claim 12, wherein the random yield comprises a random defect yield.

15. The product of claim 12, wherein the layout design includes an electronic design.

16. The product of claim 12, wherein a probability of failure for a subarray model is determined with the simulation model comprising:

P_SA=P_BSAP_RREP_RCE+P_RRE(1−

P_BSA)+P_RCE(1−

P_RRE)+P_BSA(1−

P_RCE)

Wherein the P_SA represents the probability of failure for the subarray model, the P_BSA represents the probability of failure of the two-dimensional array of bits, the P_RRE represents the probability of failure of the column of the replaceable row elements and the P_RCE represents the probability of failure of the row of replaceable the column elements.