Semiconductor chip with coil element over passivation layer

• US 7,985,653 B2
• Filed: 11/24/2008
• Issued: 07/26/2011
• Est. Priority Date: 05/18/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Lee, Wen-Chieh, Liu, Yi-Cheng, Chou, Chien-Kang, Chou, Chiu-Ming
• Primary Examiner(s): Thai; Luan C
• Application Number:
  US12/276,419
• Publication Number:
  US 20090104769A1
• Time in Patent Office: 974 Days
• Field of Search: 438/210, 438/238, 438/329, 438/381, 438/622
• US Class Current: 438/381
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01009 : Fluorine [F]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01044 : Ruthenium [Ru]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

Claims

1. A method for fabricating a semiconductor chip, comprising:

providing a silicon substrate, multiple transistors in or on said silicon substrate, a first dielectric layer over said silicon substrate, a second dielectric layer over said first dielectric layer, a first metal layer in said second dielectric layer, a third dielectric layer over said second dielectric layer and said first metal layer, wherein said third dielectric layer comprises silicon, carbon and oxygen, and wherein said third dielectric layer comprises a material with a dielectric constant less than 3, a second metal layer in said third dielectric layer, a third metal layer over said third dielectric layer and said second metal layer, a fourth dielectric layer over said third dielectric layer and said second metal layer, wherein said fourth dielectric layer comprises a portion between said second and third metal layers, and a passivation layer over said first, second, third and fourth dielectric layers and said first, second and third metal layers, wherein said passivation layer comprises a nitride layer having a thickness between 0.2 and 1.2 micrometers, wherein said second metal layer comprises an electroplated copper layer and a first adhesion layer, wherein said first adhesion layer is at a sidewall and a bottom of said electroplated copper layer, wherein said electroplated copper layer has a top surface substantially coplanar with a top surface of said third dielectric layer;

forming a first polymer layer on said passivation layer, wherein said forming said first polymer layer comprises coating a first polymer film with a photosensitive material on said passivation layer, followed by exposing and developing said coated first polymer film, followed by curing said exposed and developed first polymer film to form said first polymer layer, wherein said first polymer layer has a thickness between 5 and 20 micrometers;

forming a second polymer layer over said first polymer layer, wherein said forming said second polymer layer comprises coating a second polymer film with a photosensitive material over said first polymer layer, followed by exposing and developing said coated second polymer film, followed by curing said exposed and developed second polymer film to form said second polymer layer, wherein said second polymer layer has a thickness between 5 and 20 micrometers, wherein there is no process step of forming a metal layer between said forming said first polymer layer and said forming said second polymer layer; and

forming a fourth metal layer on said second polymer layer, wherein said forming said fourth metal layer comprises forming a second adhesion layer on said second polymer layer, followed by forming a seed layer on said second adhesion layer, followed by forming a photoresist layer on said seed layer, wherein an opening in said photoresist layer exposes a region of said seed layer, followed by electroplating a fifth metal layer over said region, followed by removing said photoresist layer, followed by removing said seed layer and said second adhesion layer not under said fifth metal layer such that said second adhesion layer is at a bottom of said fifth metal layer but not at a sidewall of said fifth metal layer.

2. The method of claim 1, wherein said forming said fourth metal layer comprises forming a coil on said second polymer layer.

3. The method of claim 1, after said forming said first polymer layer, further comprising forming a third polymer layer on said first polymer layer, followed by said forming said second polymer layer further on said third polymer layer, wherein said forming said third polymer layer comprises coating a third polymer film with a photosensitive material on said first polymer layer, followed by exposing and developing said coated third polymer film, followed by curing said exposed and developed third polymer film to form said third polymer layer, wherein said third polymer layer has a thickness between 5 and 20 micrometers.

4. The method of claim 1, wherein said electroplating said fifth metal layer comprises electroplating a gold layer having a thickness between 1 and 30 micrometers.

5. The method of claim 1, wherein said electroplating said fifth metal layer comprises electroplating a copper layer having a thickness between 1 and 30 micrometers.

6. The method of claim 1, wherein said forming said fourth metal layer, after said electroplating said fifth metal layer, further comprises electroplating a nickel layer on said fifth metal layer, followed by electroplating a gold layer on said nickel layer, followed by said removing said photoresist layer, wherein said electroplating said fifth metal layer comprises electroplating a copper layer on said region.

7. The method of claim 1, wherein said curing said exposed and developed first polymer film comprises said curing said exposed and developed first polymer film at a temperature between 250 and 450 centigrade degrees.

8. A method for fabricating a semiconductor chip, comprising:

providing a silicon substrate, multiple transistors in or on said silicon substrate, a first dielectric layer over said silicon substrate, a second dielectric layer over said first dielectric layer, a first metal layer in said second dielectric layer, a third dielectric layer over said second dielectric layer and said first metal layer, wherein said third dielectric layer comprises silicon, carbon and oxygen, and wherein said third dielectric layer comprises a material with a dielectric constant less than 3, a second metal layer in said third dielectric layer, a third metal layer over said third dielectric layer and said second metal layer, a fourth dielectric layer over said third dielectric layer and said second metal layer, wherein said fourth dielectric layer comprises a first portion between said second and third metal layers, and a passivation layer over said first, second, third and fourth dielectric layers and said first, second and third metal layers, wherein said passivation layer comprises a nitride layer having a thickness between 0.2 and 1.2 micrometers, wherein said second metal layer comprises a first adhesion layer and an electroplated copper layer, wherein said electroplated copper layer comprises a lower portion and an upper portion, and said lower and upper portions are integral, wherein said upper portion has a width greater than that of a bottom of said lower portion, wherein said upper portion has a top surface substantially coplanar with a top surface of said third dielectric layer, wherein said upper portion has a bottom surface with a first region and a second region, wherein said first and second regions are substantially coplanar at a horizontal level and separated by said electroplated copper layer, and said horizontal level is between said top surface of said third dielectric layer and a bottom surface of said third dielectric layer, wherein said first region is over a second portion of said third dielectric layer, and said second region is over a third portion of said third dielectric layer, wherein said lower portion is between said second and third portions of said third dielectric layer, wherein said first adhesion layer is at a sidewall of said lower portion, said bottom of said lower portion, said first and second regions and a sidewall of said upper portion, wherein said first adhesion layer at said bottom of said lower portion has a bottom surface substantially coplanar with said bottom surface of said third dielectric layer;

forming a first polymer layer on said passivation layer, wherein said forming said first polymer layer comprises coating a first polymer film with a photosensitive material on said passivation layer, followed by exposing and developing said coated first polymer film, followed by curing said exposed and developed first polymer film to form said first polymer layer, wherein said first polymer layer has a thickness between 5 and 20 micrometers;

forming a second polymer layer over said first polymer layer, wherein said forming said second polymer layer comprises coating a second polymer film with a photosensitive material over said first polymer layer, followed by exposing and developing said coated second polymer film, followed by curing said exposed and developed second polymer film to form said second polymer layer, wherein said second polymer layer has a thickness between 5 and 20 micrometers, wherein there is no process step of forming a metal layer between said forming said first polymer layer and said forming said second polymer layer; and

forming a fourth metal layer on said second polymer layer, wherein said forming said fourth metal layer comprises forming a second adhesion layer on said second polymer layer, followed by forming a seed layer on said second adhesion layer, followed by forming a photoresist layer on said seed layer, wherein an opening in said photoresist layer exposes a third region of said seed layer, followed by electroplating a fifth metal layer over said third region, followed by removing said photoresist layer, followed by removing said seed layer and said second adhesion layer not under said fifth metal layer such that, said second adhesion layer is at a bottom of said fifth metal layer but not at a sidewall of said fifth metal layer.

9. The method of claim 8, wherein said forming said fourth metal layer comprises forming a coil on said second polymer layer.

10. The method of claim 8, after said forming said first polymer layer, further comprising forming a third polymer layer on said first polymer layer, followed by said forming said second polymer layer further on said third polymer layer, wherein said forming said third polymer layer comprises coating a third polymer film with a photosensitive material on said first polymer layer, followed by exposing and developing said coated third polymer film, followed by curing said exposed and developed third polymer film to form said third polymer layer, wherein said third polymer layer has a thickness between 5 and 20 micrometers.

11. The method of claim 8, wherein said electroplating said fifth metal layer comprises electroplating a gold layer having a thickness between 1 and 30 micrometers.

12. The method of claim 8, wherein said electroplating said fifth metal layer comprises electroplating a copper layer having a thickness between 1 and 30 micrometers.

13. The method of claim 8, wherein said forming said fourth metal layer, after said electroplating said fifth metal layer, further comprises electroplating a nickel layer on said fifth metal layer, followed by electroplating a gold layer on said nickel layer, followed by said removing said photoresist layer, wherein said electroplating said fifth metal layer comprises electroplating a copper layer on said third region.

14. The method of claim 8, wherein said curing said exposed and developed first polymer film comprises said curing said exposed and developed first polymer film at a temperature between 250 and 450 centigrade degrees.

15. A method for fabricating a semiconductor chip, comprising:

providing a silicon substrate, multiple transistors in or on said silicon substrate, a first dielectric layer over said silicon substrate, a second dielectric layer over said first dielectric layer, a first metal layer in said second dielectric layer, a third dielectric layer over said second dielectric layer and said first metal layer, wherein said third dielectric layer comprises silicon, carbon and oxygen, and wherein said third dielectric layer comprises a material with a dielectric constant less than 3, a second metal layer in said third dielectric layer, a third metal layer over said third dielectric layer and said second metal layer, a fourth dielectric layer over said third dielectric layer and said second metal layer, wherein said fourth dielectric layer comprises a portion between said second and third metal layers, and a passivation layer over said first, second, third and fourth dielectric layers and said first, second and third metal layers, wherein said passivation layer comprises a nitride layer having a thickness between 0.2 and 1.2 micrometers, wherein an upper opening and a lower opening are in said third dielectric layer, and said upper opening is over and aligned with said lower opening, wherein said upper opening has a first sidewall and a second sidewall opposite to said first sidewall of said upper opening, wherein a width between said first and second sidewalls of said upper opening is greater than that of a bottom of said lower opening, wherein said second metal layer comprises a first adhesion layer on said bottom of said lower opening, a sidewall of said lower opening and said first and second sidewalls of said upper opening and an electroplated copper layer over said first adhesion layer, wherein said electroplated copper layer comprises a lower portion in said lower opening and an upper portion in said upper opening, wherein said lower and upper portions are integral, wherein said upper portion is over and aligned with said lower portion, wherein said upper portion has a top surface substantially coplanar with a top surface of said third dielectric layer, wherein said first adhesion layer is at a sidewall and a bottom of said lower portion and at a sidewall of said upper portion;

forming a first polymer layer on said passivation layer, wherein said forming said first polymer layer comprises coating a first polymer film with a photosensitive material on said passivation layer, followed by exposing and developing said coated first polymer film, followed by curing said exposed and developed first polymer film to form said first polymer layer, wherein said first polymer layer has a thickness between 5 and 20 micrometers;

forming a second polymer layer over said first polymer layer, wherein said forming said second polymer layer comprises coating a second polymer film with a photosensitive material over said first polymer layer, followed by exposing and developing said coated second polymer film, followed by curing said exposed and developed second polymer film to form said second polymer layer, wherein said second polymer layer has a thickness between 5 and 20 micrometers, wherein there is no process step of forming a metal layer between said forming said first polymer layer and said forming said second polymer layer; and

forming a fourth metal layer on said second polymer layer, wherein said forming said fourth metal layer comprises forming a second adhesion layer on said second polymer layer, followed by forming a seed layer on said second adhesion layer, followed by forming a photoresist layer on said seed layer, wherein an opening in said photoresist layer exposes a region of said seed layer, followed by electroplating a fifth metal layer over said region, followed by removing said photoresist layer, followed by removing said seed layer and said second adhesion layer not under said fifth metal layer such that, said second adhesion layer is at a bottom of said fifth metal layer but not at a sidewall of said fifth metal layer.

16. The method of claim 15, wherein said forming said fourth metal layer comprises forming a coil on said second polymer layer.

17. The method of claim 15, wherein said electroplating said fifth metal layer comprises electroplating a gold layer having a thickness between 1 and 30 micrometers.

18. The method of claim 15, wherein said electroplating said fifth metal layer comprises electroplating a copper layer having a thickness between 1 and 30 micrometers.

19. The method of claim 15, wherein said forming said fourth metal layer, after said electroplating said fifth metal layer, further comprises electroplating a nickel layer on said fifth metal layer, followed by electroplating a gold layer on said nickel layer, followed by said removing said photoresist layer, wherein said electroplating said fifth metal layer comprises electroplating a copper layer on said region.

20. The method of claim 15, wherein said curing said exposed and developed first polymer film comprises said curing said exposed and developed first polymer film at a temperature between 250 and 450 centigrade degrees.

21. A method for fabricating a semiconductor chip, comprising:

providing a silicon substrate, multiple transistors in or on said silicon substrate, a first dielectric layer over said silicon substrate, a first metal layer over said silicon substrate and said first dielectric layer, a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, wherein said second metal layer is connected to said first metal layer through an opening in said second dielectric layer, and a passivation layer over said first and second dielectric layers and said first and second metal layers, wherein said passivation layer comprises a nitride;

forming a metallization structure over said passivation layer, wherein said metallization structure comprises a metal trace and a metal bump directly on a top surface of said metal trace, wherein said metal bump comprises a first electroplated copper layer; and

after said forming said metallization structure, forming a polymer layer over said passivation layer and said top surface of said metal trace whereby said polymer layer has no portion between said top surface of said metal trace and said metal bump, said metal bump has a top surface at a first horizontal level higher than a second horizontal level of a top surface of said polymer layer, said metal bump has a portion at a same horizontal level as said polymer layer, and said metal bump is spaced apart from said polymer layer.

22. The method of claim 21, wherein said polymer layer has a thickness between 5 and 20 micrometers.

23. The method of claim 21, wherein said metal trace comprises an adhesion layer, a copper-containing seed layer on said adhesion layer, and a second electroplated copper layer on said copper-containing seed layer, wherein said second electroplated copper layer has a thickness between 1 and 30 micrometers.

24. The method of claim 23, wherein said first electroplated copper layer is directly on said second electroplated copper layer.

25. The method of claim 21, wherein said first metal layer comprises electroplated copper.

26. The method of claim 21, wherein said first metal layer comprises aluminum.

27. The method of claim 21, wherein said metal bump has a thickness between 1 and 500 micrometers.

28. The method of claim 21, wherein said forming said polymer layer comprises an exposing process and a developing process.

29. The method of claim 21, wherein said forming said polymer layer comprises a coating process.