Method of making a contact in a semiconductor device

• US 7,985,676 B2
• Filed: 01/25/2010
• Issued: 07/26/2011
• Est. Priority Date: 12/13/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Knoefler, Roman, Schroeder, Uwe Paul, Klee, Veit
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): SNOW, COLLEEN ERIN
• Application Number:
  US12/693,231
• Publication Number:
  US 20100124820A1
• Time in Patent Office: 547 Days
• Field of Search: 438/636, 438/637, 438/692, 438/735, 438/736, 438/738, 438/739, 438/761, 438/763, 257/E21.585
• US Class Current: 438/637
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.

Claims

1. A method for forming a semiconductor device, the method comprising:

after forming a gate and a source/drain region of a transistor, forming an etch stop layer over a conductive region;

forming an insulating layer over the etch stop layer;

forming a pattern transfer layer adjacent an upper portion of the insulating layer, the pattern transfer layer being patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed;

forming a conductive mask material over the insulating layer, the conductive mask material being self-aligned with the pattern transfer layer, wherein forming a conductive mask material comprises;

depositing a layer of the conductive mask material, and

performing a chemical mechanical polish step to remove any conductive mask material from over portions of the pattern transfer layer;

removing remaining portions of the pattern transfer layer; and

forming a contact hole having continuously vertical sidewalls by etching recesses in the insulating layer using the conductive mask material as a mask.

2. The method of claim 1, wherein forming a pattern transfer layer comprises depositing a layer over the insulating layer and etching the deposited layer.

3. The method of claim 2, wherein depositing a layer comprises depositing a silicon nitride layer.

4. The method of claim 1, wherein forming a pattern transfer layer comprises etching an upper portion of the insulating layer.

5. The method of claim 1, wherein the conductive mask material comprises tungsten.

6. The method of claim 1, further comprising filling the contact hole with a conductive material.

7. The method of claim 6, further comprising removing the conductive mask material after filling the contact hole with the conductive material.

8. The method of claim 1, wherein the conductive region comprises doped silicon.

9. The method of claim 1, wherein the conductive region comprises a metal.

10. The method of claim 1, further comprising:

forming a resist layer separate and distinct from and over said pattern transfer layer; and

removing portions of the resist layer so as to leave resist on said pattern transfer layer according to a selected pattern, the resist layer being patterned in the reverse tone of the layout of recesses to be formed in the insulating layer such that the resist layer remains over regions where the recesses are to be formed.

11. The method of claim 1, wherein forming a contact hole comprises etching through the insulating layer and the etch stop layer.

12. A method of forming a semiconductor device, the method comprising:

forming a transistor having a gate and a source/drain region in a semiconductor body;

forming an insulating layer over the semiconductor body including over the transistor;

depositing a pattern transfer layer over the insulating layer;

depositing a antireflective coating (ARC) layer over the pattern transfer layer;

forming a resist layer over the ARC layer;

patterning the resist layer and the ARC layer to expose portions of the pattern transfer layer;

removing the exposed portions of the pattern transfer layer to expose portions of the insulating layer;

forming a conductive masking layer over the exposed portions of the insulating layer;

removing remaining portions of the pattern transfer layer;

etching a contact hole in the insulating layer using the conductive masking layer as a mask;

filling the contact hole with a conductor, the conductor being electrically coupled to the transistor, wherein filling the contact hole comprises forming a butted contact that electrically couples both the gate and the source/drain region; and

removing the conductive masking layer, wherein removing the conductive masking layer comprises performing a chemical mechanical polish or a reactive ion etch.

13. The method of claim 12, wherein depositing the conductive masking layer comprises depositing tungsten.

14. The method of claim 12, wherein the conductive masking layer is removed before forming the conductor in the contact hole.

15. The method of claim 12, wherein the conductive masking layer is removed after forming the conductor in the contact hole.

16. The method of claim 12, wherein the conductor comprises tungsten.

17. The method of claim 16, further comprising forming a conductive liner in the contact hole before filling the contact hole with the conductor.

18. The method of claim 17, wherein the conductive liner comprises a layer of titanium nitride overlying a layer of titanium.

19. The method of claim 12, wherein the butted contact physically contacts a first silicide region on the gate and a second silicide region on the source/drain region.

20. A method of forming a semiconductor device, the method comprising:

forming a transistor having a gate and a source/drain region in a semiconductor body;

forming an etch stop layer over the semiconductor body including over the transistor;

forming a blanket insulating layer over the etch stop layer;

depositing a pattern transfer layer over the insulating layer;

depositing a antireflective coating (ARC) layer over the pattern transfer layer;

forming a resist layer over the ARC layer;

patterning the resist layer and the ARC layer to expose portions of the pattern transfer layer;

removing the exposed portions of the pattern transfer layer to expose portions of the insulating layer;

forming a conductive masking layer over the exposed portions of the insulating layer;

removing remaining portions of the pattern transfer layer;

etching a contact hole in the blanket insulating layer using the conductive masking layer as a mask;

filling the contact hole with a conductor, the conductor being electrically coupled to the transistor; and

removing the conductive masking layer, wherein removing the conductive masking layer comprises performing a chemical mechanical polish or a reactive ion etch.

21. The method of claim 20, wherein filling the contact hole comprises forming a butted contact that electrically couples both the gate and the source/drain region.

22. The method of claim 20, wherein removing remaining portions of the pattern transfer layer and etching a contact hole comprising etching through the insulating layer and the etch stop layer are performed in a single etching step.