Stacked bit line dual word line nonvolatile memory

• US 7,985,989 B2
• Filed: 06/01/2009
• Issued: 07/26/2011
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang-Lan
• Primary Examiner(s): Smith; Bradley K
• Assistant Examiner(s): KARIMY, MOHAMMAD TIMOR
• Application Number:
  US12/475,839
• Publication Number:
  US 20090236639A1
• Time in Patent Office: 785 Days
• Field of Search: 257/209, 257/E29.166
• US Class Current: 257/209
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

Claims

1. A memory device, comprising:

a substrate having a substrate surface;

a plurality of polysilicon lines substantially orthogonal to the substrate surface;

first and second conductive lines over the substrate adjacent respective first and second side surface areas on the plurality of polysilicon lines;

a plurality of first level memory cells between the first conductive line and the first side surface areas of the plurality of polysilicon lines;

a plurality of second level memory cells between the second conductive line and the second side surface areas of the plurality of polysilicon lines, wherein the first level memory cells are over the second level memory cells; and

a plurality of third conductor lines orthogonal to the first and second conductor lines and to the plurality of polysilicon lines, and coupled to respective polysilicon lines in the plurality of polysilicon lines.

2. The memory device of claim 1, wherein the first and second conductive lines are arranged in respective first and second levels above the substrate.

3. The memory device of claim 1, wherein the first and second conductive lines comprise polysilicon having a conductivity type opposite that of the plurality of polysilicon lines.

4. The memory device of claim 1, wherein the second conductive line is directly above the first conductive line.

5. The memory device of claim 1, wherein said first level memory cells and said second level memory cells comprise non-volatile memory cells.

6. The memory device of claim 1, wherein said first level memory cells and said second level memory cells comprise anti-fuse elements.

7. A memory device, comprising:

a substrate;

a plurality of word lines and a plurality of bit lines over the substrate, the bit lines in the plurality of bit lines being disposed in a plurality of levels;

a plurality of plugs electrically coupled with the word lines;

a first memory cell disposed on a sidewall of one of the plugs in the plurality of plugs, and between one of the bit lines in the plurality of bit lines and said one of the plugs; and

a second memory cell disposed on a sidewall of another one of the plugs in the plurality of plugs, and between another one of the bit lines in the plurality of bit lines and said another one of the plugs, wherein the first and second memory cells are not at the same level.

8. The memory device of claim 7, wherein the plurality of bit lines include a first set of bit lines and a second set of bit lines arranged in respective first and second levels above the substrate.

9. The memory device of claim 7, wherein the plurality of bit lines comprise polysilicon having a conductivity type opposite that of the plurality of plugs.

10. The memory device of claim 7, wherein the second set of bit lines is disposed directly above the first set of bit lines.

11. The memory device of claim 7, wherein said first and second memory cells comprise non-volatile memory cells.

12. The memory device of claim 7, wherein said first and second memory cells comprise anti-fuse elements.

13. A memory device, comprising:

a substrate;

first and second word lines over the substrate;

a first plug coupled to the first word line, and orthogonal to the first word line and the substrate;

a second plug coupled to the second word line, and orthogonal to the second word line and the substrate;

a first plurality of memory cells disposed on a first side wall beside the first plug; and

a second plurality of memory cells disposed on a second sidewall beside the second plug, wherein the first word line is over the second word line.

14. The memory device of claim 13, wherein said first and second memory cells comprise non-volatile memory cells.

15. The memory device of claim 13, wherein said first and second memory cells comprise anti-fuse elements.