Circuit configurations having four terminal devices

• US 7,986,167 B2
• Filed: 08/23/2010
• Issued: 07/26/2011
• Est. Priority Date: 05/11/2006
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Kapoor, Ashok Kumar
• Primary Examiner(s): Le; Don P
• Application Number:
  US12/861,659
• Publication Number:
  US 20100315128A1
• Time in Patent Office: 337 Days
• Field of Search: 326/37, 326/38, 326101-104, 326/112, 326/119, 326/121
• US Class Current: 326/121
• CPC Class Codes: H01L 2029/7857 of the accumulation type
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/8086 Thin film JFET's
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/09403 using junction field-effect transistors H03K19/096 takes precedence

Abstract

Circuits using four terminal transistors are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal transistors operating in a linear or nonlinear mode.

Claims

1. A circuit that alters the conductivity of transistor channels by operation of two independently controlled control terminals, comprising:

at least one input node;

at least one output node; and

a plurality of transistors each including a first gate, a second gate independently operable from the first gate, and a channel region between the first gate and second gate, the channel region connecting a source region to a drain region both of a same conductivity type, each transistor having a second gate coupled to receive an enable signal that increases the conductivity of the channel in a first mode of operation and decreases the conductivity of the channel in a second mode of operation as compared to the first mode of operation.

2. The circuit of claim 1, wherein

the plurality of transistors includes first transistors of a first conductivity type having second gates coupled to receive one potential in the first mode of operation and another potential in the second mode of operation.

3. The circuit of claim 1, wherein:

the plurality of transistors includes first transistors of a first conductivity type and second transistors of a second conductivity type, the second transistors having second gates coupled to receive one potential in the first mode of operation and another potential in the second mode of operation.

4. The circuit of claim 3, wherein:

the first transistors have second gates coupled to receive a first voltage in the first mode of operation and a second voltage in the second mode of operation; and

the second transistors have second gates coupled to receive a third voltage in the first mode of operation and a fourth voltage in the second mode of operation.

5. The circuit of claim 1, further including:

a low power logic section configured to provide at least the enable signal in response to predetermined inputs; and

switching circuit that selectively apply the enable signal the second gates of the transistors.

6. The circuit of claim 5, wherein:

the low power logic section configured to generates input signals applied to first gates of the transistors.

7. The logic circuit of claim 1, wherein:

the first gates are top gates formed over the channel of their respective transistors and the second gates are bottom gates formed below the channels of the respective transistors.

8. A circuit that alters the conductivity of a transistor channel by operation of two independently controlled control terminals, comprising:

a plurality of transistors each including a first gate and a second gate independently operable from the first gate, the plurality of transistor including

a plurality of precharge transistors having source-drain paths coupled to a power supply node, and a first gate and second gate connected to at least one clock signal that periodically varies between logic levels, and

a plurality of logic transistors having source-drain path coupled in series with at least one source-drain path of a precharge transistor, a first gate coupled to a first input node and a second gate coupled to a second input node.

9. The circuit of claim 8, wherein:

the plurality of precharge transistors includes first precharge transistors of a first conductivity type coupled between the first power supply node and the logic transistors.

10. The circuit of claim 9, wherein:

the plurality of precharge transistors includes second precharge transistors of a second conductivity type coupled between a second power supply node and the logic transistors.

11. The circuit of claim 8, wherein:

the plurality of logic transistors includes at least

a first logic transistor having its first gate coupled to receive a first input signal and its second gate coupled to receive a second input signal, and

a second logic transistor having its first gate coupled to receive a third input signal, and its second gate coupled to receive the second input signal.

12. The circuit of claim 8, further including:

an output node coupled between a source-drain path of one precharge transistor and one logic transistor; and

a driver circuit having an input coupled to the output node and output that provides a logic output signal, the driver circuit configured to generate a logic output signal in response to a potential at the output node.

13. A circuit having four terminal devices, comprising:

at least one first transistor of a first conductivity type having a first gate coupled to a first input node, a second gate coupled to a second node, and a source-drain path coupled between a first power supply node and an internal node; and

at least one second transistor of a second conductivity type having a gate coupled to the first input node, and a source-drain path coupled between the internal node and a second power supply node.

14. The circuit of claim 13, wherein:

the at least one second transistor includes a first gate coupled to the first input node and a second gate coupled to the second node;

wherein the second node is a second input node.

15. The circuit of claim 13, wherein:

the at least one second transistor includes a first gate coupled to the first input node and a second gate coupled to a third input node.

16. The circuit of claim 13, wherein:

the at least one first transistor includes a plurality of first transistors having source-drain paths coupled in parallel with one another between the first power supply node and the internal node; and

the at least one second transistor includes a plurality of second transistors having source-drain paths coupled in series with one another between the second power supply node and the internal node.

17. The circuit of claim 13, wherein:

at least one of the first or second transistors is a single gate depletion mode device that provides a low impedance source-drain path in response to either its top gate or bottom gate having predetermined logic levels.

18. The circuit of claim 13, wherein:

at least one of the first or second transistors is a single gate enhancement mode device that provides a low impedance source-drain path in response to only both its top gate and bottom gate being at predetermined logic levels.

19. The circuit of claim 13, wherein:

at least one first transistor includes

a first memory transistor having a source-drain path coupled between the first power supply node and a first internal node, and at least one gate coupled to a second internal node; and

a second memory transistor having a source-drain path coupled between the first power supply node and the second internal node, and at least one gate coupled to the first internal node.

20. The circuit of claim 19, wherein:

at least one second transistor includes

a third memory transistor having a source-drain path coupled between the second power supply node and the first internal node, and at least one gate coupled to the second internal node; and

a fourth memory transistor having a source-drain path coupled between the second power supply node and the second internal node, and at least one gate coupled to the first internal node.