Spread spectrum control PLL circuit and its start-up method

• US 7,986,175 B2
• Filed: 03/18/2008
• Issued: 07/26/2011
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Komatsu, Yoshihide, Ebuchi, Tsuyoshi, Yamamoto, Michiyo
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Cole; Brandon S
• Application Number:
  US12/595,008
• Publication Number:
  US 20100127739A1
• Time in Patent Office: 1,225 Days
• Field of Search: 327/141, 327144-163, 331/1.A, 331 15- 17, 375373-376
• US Class Current: 327/147
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A calibration circuit (19) adjusts at least one of one of a charging current of a charge pump circuit (12) and a capacitance value of a filter capacitor in a loop filter circuit (13) and a gain of a voltage controlled oscillator (14), depending on a frequency of a reference clock signal input to a calibration circuit (10).

Claims

1. A spread spectrum control PLL circuit for outputting a spread spectrum clock signal based on an input reference clock signal, comprising:

a charge pump circuit configured to switch charging and discharging of a charging current, depending on a phase difference between a feedback clock signal based on an output clock signal of the PLL circuit and the reference clock signal;

a loop filter circuit having a filter capacitor which is charged and discharged using the charging current output from the charge pump circuit;

a voltage controlled oscillator configured to oscillate at a frequency depending on an input control voltage; and

a calibration circuit configured to adjust at least one of one of the charging current of the charge pump circuit and a capacitance value of the filter capacitor and a gain of the voltage controlled oscillator, depending on a frequency of the reference clock signal,

wherein the voltage controlled oscillator includes;

a selector circuit configured to select as the control voltage one from a first voltage, a second voltage, and an output voltage of the loop filter circuit, and

the calibration circuit includes

a timer circuit configured to measure a period of time depending on the frequency of the reference clock signal;

a counter circuit configured to count pulses of the output clock signal of the PLL circuit or a frequency-divided clock signal thereof during a period of time when the timer circuit is operating; and

a control circuit configured to control the selector circuit to adjust the gain of the voltage controlled oscillator so that a difference in count value of the counter circuit between when the first voltage is input to the voltage controlled oscillator and when the second voltage is input to the voltage controlled oscillator approaches a target value, and

wherein

the calibration circuit includes;

a first memory circuit and a second memory circuit configured to store the count value of the counter circuit which is obtained when the first voltage is input to the voltage controlled oscillator and when the second voltage is input to the voltage controlled oscillator, respectively;

a subtractor configured to calculate a difference between the count values stored in the first and second memory circuits; and

a comparator configured to compare an output of the subtractor with the target value, and

the control circuit adjusts the gain of the voltage controlled oscillator based on an output of the comparator.

2. The spread spectrum control PLL circuit of claim 1, wherein

the calibration circuit outputs a digital control signal to switch the gain of the voltage controlled oscillator,

the comparator outputs, as a result of the comparison, 1-bit information indicating whether or not the output of the subtractor is larger than the target value, and

the control circuit determines a value of the digital control signal by binary search based on the result of the comparison by the comparator.

3. A spread spectrum control PLL circuit for outputting a spread spectrum clock signal based on an input reference clock signal, comprising:

a charge pump circuit configured to switch charging and discharging of a charging current, depending on a phase difference between a feedback clock signal based on an output clock signal of the PLL circuit and the reference clock signal;

a loop filter circuit having a filter capacitor which is charged and discharged using the charging current output from the charge pump circuit;

a voltage controlled oscillator configured to oscillate at a frequency depending on an input control voltage; and

a calibration circuit configured to adjust at least one of one of the charging current of the charge pump circuit and a capacitance value of the filter capacitor and a gain of the voltage controlled oscillator, depending on a frequency of the reference clock signal,

wherein the voltage controlled oscillator includes;

a selector circuit configured to select as the control voltage one from a first voltage, a second voltage, and an output voltage of the loop filter circuit, and

the calibration circuit includes;

a timer circuit configured to measure a period of time depending on the frequency of the reference clock signal;

a counter circuit configured to count pulses of the output clock signal of the PLL circuit or a frequency-divided clock signal thereof during a period of time when the timer circuit is operating; and

a control circuit configured to control the selector circuit to adjust the gain of the voltage controlled oscillator so that a difference in count value of the counter circuit between when the first voltage is input to the voltage controlled oscillator and when the second voltage is input to the voltage controlled oscillator approaches a target value, and

wherein the timer circuit counts pulses of the reference clock signal or a frequency-divided clock signal thereof to a predetermined number.

4. The spread spectrum control PLL circuit of claim 3, wherein at least one of the predetermined number, the first voltage, the second voltage and the target value is variable.

5. A spread spectrum control PLL circuit for outputting a spread spectrum clock signal based on an input reference clock signal, comprising:

a charge pump circuit configured to switch charging and discharging of a charging current, depending on a phase difference between a feedback clock signal based on an output clock signal of the PLL circuit and the reference clock signal;

a loop filter circuit having a filter capacitor which is charged and discharged using the charging current output from the charge pump circuit;

a voltage controlled oscillator configured to oscillate at a frequency depending on an input control voltage; and

a calibration circuit configured to adjust at least one of one of the charging current of the charge pump circuit and a capacitance value of the filter capacitor and a gain of the voltage controlled oscillator, depending on a frequency of the reference clock signal,

wherein the calibration circuit includes;

an oscillator configured to have a replica charge pump circuit which is a replica of the charge pump circuit and a second filter capacitor which is charged and discharged using a charging current output from the replica charge pump circuit, and oscillate at a frequency depending on the charging current of the replica charge pump circuit and a capacitance value of the second filter capacitor;

a timer circuit configured to measure a period of time depending on the frequency of the reference clock signal;

a counter circuit configured to count pulses of an output clock signal of the oscillator or a frequency-divided clock signal thereof during a period of time when the timer circuit is operating; and

a control circuit configured to adjust the charging current of the replica charge pump circuit so that a count value of the counter circuit approaches a target value, and

the control circuit uses a common control signal to set the charging current for each of the charge pump circuit and the replica charge pump circuit.

6. The spread spectrum control PLL circuit of claim 5, wherein

the calibration circuit includes:

a comparator configured to compare the count value of the counter circuit with the target value, and

the control circuit adjusts the charging current of the replica charge pump circuit based on an output of the comparator.

7. The spread spectrum control PLL circuit of claim 6, wherein

the calibration circuit outputs a digital control signal to switch the charging current,

the comparator outputs, as a result of the comparison, 1-bit information indicating whether or not the count value of the counter circuit is larger than the target value, and

the control circuit determines a value of the digital control signal by binary search based on the result of the comparison by the comparator.

8. The spread spectrum control PLL circuit of claim 5, wherein the timer circuit counts pulses of the reference clock signal or a frequency-divided clock signal thereof.

9. The spread spectrum control PLL circuit of claim 8, wherein at least one of the predetermined number and the target value is variable.

10. A spread spectrum control PLL circuit for outputting a spread spectrum clock signal based on an input reference clock signal, comprising:

a charge pump circuit configured to switch charging and discharging of a charging current, depending on a phase difference between a feedback clock signal based on an output clock signal of the PLL circuit and the reference clock signal;

a loop filter circuit having a filter capacitor which is charged and discharged using the charging current output from the charge pump circuit;

a voltage controlled oscillator configured to oscillate at a frequency depending on an input control voltage; and

a calibration circuit configured to adjust at least one of one of the charging current of the charge pump circuit and a capacitance value of the filter capacitor and a gain of the voltage controlled oscillator, depending on a frequency of the reference clock signal,

wherein the calibration circuit includes;

an oscillator configured to have a second charge pump circuit, and a replica filter capacitor which is a replica of the filter capacitor and is charged and discharged using a charging current output from the second charge pump circuit, and oscillate at a frequency depending on the charging current of the second charge pump circuit and a capacitance value of the replica filter capacitor;

a timer circuit configured to measure a period of time depending on the frequency of the reference clock signal;

a counter circuit configured to count pulses of an output clock signal of the oscillator or a frequency-divided clock signal thereof during a period of time when the timer circuit is operating; and

a control circuit configured to adjust the capacitance value of the replica filter capacitor so that a count value of the counter circuit approaches a target value, and

the control circuit uses a common control signal to set the capacitance values of the filter capacitor and the replica filter capacitor.

11. The spread spectrum control PLL circuit of claim 10, wherein

the calibration circuit includes:

a comparator configured to compare the count value of the counter circuit with the target value, and

the control circuit adjusts the capacitance value of the replica filter capacitor based on an output of the comparator.

12. The spread spectrum control PLL circuit of claim 11, wherein

the calibration circuit outputs a digital control signal to switch the capacitance value of the filter capacitor,

the comparator outputs, as a result of the comparison, 1-bit information indicating whether or not the count value of the counter circuit is larger than the target value, and

the control circuit determines a value of the digital control signal by binary search based on the result of the comparison by the comparator.

13. The spread spectrum control PLL circuit of claim 10, wherein the timer circuit counts pulses of the reference clock signal or a frequency-divided clock signal thereof to a predetermined number.

14. The spread spectrum control PLL circuit of claim 13, wherein at least one of the predetermined number and the target value is variable.