Analog-digital conversion cell and analog-digital converter

• US 7,986,258 B2
• Filed: 02/02/2010
• Issued: 07/26/2011
• Est. Priority Date: 08/03/2007
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Takayama, Takeshi, Gotoh, Kunihiko
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US12/698,853
• Publication Number:
  US 20100134337A1
• Time in Patent Office: 539 Days
• Field of Search: 341/155, 341/144, 341/161, 341/172
• US Class Current: 341/155
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

There is provided an analog-digital conversion cell being an analog-digital conversion cell that performs an N-bit analog-digital conversion (where N is a natural number) and including: a comparison circuit (202) comparing an analog input signal VI based on a plurality of reference voltages and outputting a first digital code DA selected from Q digital codes (where Q is a natural number equal to or more than 2^N+1 and equal to or less than 2^N+1−1) in accordance with a size of the analog input signal VI; a first logic operation circuit (203) outputting a second digital code DB selected from Q digital codes, which is expressed by DB=DA×KA+DB0 where a constant KA is a decimal number satisfying a condition of 1<KA<2 and DB0 is a constant, based on the first digital code DA; and an analog operation circuit (201) outputting an analog output signal VO expressed by VO=A×(VI−DA×KA×(VR/A)) where A and VR are constants, based on the first digital code DA and the analog input signal VI.

Claims

1. An analog-digital conversion cell being an analog-digital conversion cell that performs an N-bit analog-digital conversion (where N is a natural number), the analog-digital conversion cell comprising:

a comparison circuit comparing an analog input signal VI based on a plurality of reference voltages and outputting a first digital code DA selected from Q digital codes (where Q is a natural number equal to or more than 2^N+1 and equal to or less than 2^N+1−

1) in accordance with a size of the analog input signal VI;

a first logic operation circuit outputting a second digital code DB selected from Q digital codes, which is expressed by DB=DA×

KA+DB0 where a constant KA is a decimal number satisfying a condition of 1<

KA<

2 and DB0 is a constant, based on the first digital code DA; and

an analog operation circuit outputting an analog output signal VO expressed by VO=A×

(VI−

DA×

KA×

(VR/A)) where A and VR are constants, based on the first digital code DA and the analog input signal VI.

2. The analog-digital conversion cell according to claim 1, wherein

the plural reference voltages of said comparison circuit are ±

KA×

VR×

C/2^N+1, and when the Q is an odd number, C is ±

1, ±

3, . . . , ±

(Q−

2), and when the Q is an even number, C is 0, ±

2, ±

4, . . . , ±

(Q−

2).

3. The analog-digital conversion cell according to claim 1, wherein

the first digital code DA is selected from Q digital codes, and the first digital code DA is 0, ±

1, ±

2, . . . , ±

(Q−

1)/2 when the Q is an odd number, and the first digital code DA is ±

½

, ±

3/2, . . . , ±

(Q−

3)/2 when the Q is an even number.

4. The analog-digital conversion cell according to claim 1, wherein

the constant KA is equal to or more than (2^N−

¾

)/(2^N−

1) and equal to or less than 3/2 when the Q is an odd number, and the constant KA is equal to or more than (2^N−

¾

)/(2^N−

3/2) and equal to or less than 3/2 when the Q is an even number.

5. The analog-digital conversion cell according to claim 1, wherein

the constant KA is 5/4 and the second digital code DB is represented by three values of +1.01, 0.00, and −

1.01 in a binary number, or the constant KA is 3/2 and the second digital code DB is represented by three values of +1.1, 0.0, and −

1.1 in a binary number, or the constant KA is 21/16 and the second digital code DB is represented by three values of +1.0101, 0.0000, and −

1.0101 in a binary number.

6. The analog-digital conversion cell according to claim 1, wherein

said analog operation circuit includes two or more capacitances for sampling the analog input signal VI and one operational amplifier, and when outputting the analog output signal VO, at least the one or more capacitances out of the capacitances is/are connected to an output of the operational amplifier and the other capacitance/capacitances is/are connected to a voltage in accordance with the first digital code DA.

7. The analog-digital conversion cell according to claim 1, wherein

said analog operation circuit includes:

a first capacitance;

a second capacitance;

an operational amplifier in which a voltage of an interconnection point of first terminals of the first and second capacitances is input, and outputting the analog output signal VO;

a digital-analog conversion cell outputting a first analog signal to a second terminal of the second capacitance based on the first digital code DA;

a first switch connecting a second terminal of the first capacitance to either a terminal of the analog input signal VI or an output terminal of the operational amplifier;

a second switch connecting the second terminal of the second capacitance to the terminal of the analog input signal VI; and

a third switch connecting the interconnection point of the first terminals of the first and second capacitances and a reference potential.

8. An analog-digital converter comprising:

two or more analog-digital conversion cells; and

a second logic operation circuit outputting a digital output signal that is an analog-digital conversion result based on a second digital code that each of said analog-digital conversion cells outputs, and wherein

at least one or more out of said two or more analog-digital conversion cells is/are the analog-digital conversion cell according to claim 1.

9. The analog-digital converter according to claim 8, wherein

out of said two or more analog-digital conversion cells, said analog-digital conversion cell at an initial stage is the analog-digital conversion cell according to claim 1.

10. The analog-digital converter according to claim 9, wherein

said analog-digital conversion cells at a second stage and thereafter are an analog-digital conversion cell performing an N-bit analog-digital conversion (where N is a natural number), and include;

a comparison circuit comparing an analog input signal VI based on a plurality of reference voltages and outputting a first digital code DA selected from Q digital codes (where Q is a natural number equal to or more than 2^N+1 and equal to or less than 2^N+1−

1) in accordance with a size of the analog input signal VI;

a first logic operation circuit outputting a second digital code DB selected from Q digital codes, which is expressed by DB=DA×

KA+DB0 where a constant KA is a decimal number satisfying a condition of 1<

KA<

2 or KA<

1 and DB0 is a constant, based on the first digital code DA; and

an analog operation circuit outputting an analog output signal VO expressed by VO=A×

(VI−

DA×

KA×

(VR/A)) where A and VR are constants, based on the first digital code DA and the analog input signal VI, and

the comparison circuit has Q-2 or less comparators.

11. The analog-digital converter according to claim 8, wherein

one of said analog-digital conversion cells at a second stage and thereafter out of said two or more analog-digital conversion cells is an analog-digital conversion cell performing an N-bit analog-digital conversion (where N is a natural number), and includes;

a comparison circuit comparing an analog input signal VI based on a plurality of reference voltages and outputting a first digital code DA selected from Q digital codes (where Q is a natural number equal to or more than 2^N+1 and equal to or less than 2^N+1−

1) in accordance with a size of the analog input signal VI;

a first logic operation circuit outputting a second digital code DB selected from Q digital codes, which is expressed by DB=DA×

KA+DB0 where a constant KA is 1 and DB0 is a constant, based on the first digital code DA; and

an analog operation circuit outputting an analog output signal VO expressed by VO=A×

(VI−

DA×

KA×

(VR/A)) where A and VR are constants, based on the first digital code DA and the analog input signal VI.

12. The analog-digital converter according to claim 8, wherein

one of said analog-digital conversion cells at a second stage and thereafter out of said two or more analog-digital conversion cells is an analog-digital conversion cell performing an N-bit analog-digital conversion (where N is a natural number that is equal to or more than 2), and includes;

a comparison circuit comparing an analog input signal VI based on a plurality of reference voltages and outputting a first digital code DA selected from Q digital codes (where Q is a natural number equal to or more than 2^N+1 and equal to or less than 2^N+1−

1) in accordance with a size of the analog input signal VI;

a first logic operation circuit outputting a second digital code DB selected from Q digital codes, which is expressed by DB=DA×

KA+DB0 where KA and DB0 are constants, based on the first digital code DA; and

an analog operation circuit outputting an analog output signal VO expressed by VO=A×

(VI−

DA×

KA×

(VR/A)) where A and VR are constants, based on the first digital code DA and the analog input signal VI.

13. The analog-digital converter according to claim 8, wherein

one of said analog-digital conversion cells at a second stage and thereafter out of said two or more analog-digital conversion cells is an analog-digital conversion cell performing an N-bit analog-digital conversion (where N is a natural number), and includes;

a comparison circuit comparing an analog input signal VI based on a plurality of reference voltages and outputting a first digital code DA selected from Q digital codes (where Q is a natural number equal to or more than 2^N+1 and equal to or less than 2^N+1−

1) in accordance with a size of the analog input signal VI;

a first logic operation circuit outputting a second digital code DB selected from Q digital codes, which is expressed by DB=DA×

KA+DB0 where a constant KA is less than 1 and DB0 is a constant, based on the first digital code DA; and

an analog operation circuit outputting an analog output signal VO expressed by VO=A×

(VI−

DA×

KA×

(VR/A)) where A and VR are constants, based on the first digital code DA and the analog input signal VI.

14. The analog-digital converter according to claim 13, wherein

in said analog-digital conversion cell at a subsequent stage,

the constant A is 2^N,

the plural reference voltages of the comparison circuit are ±

KA×

VR×

C/2^N+1, and when the Q is an odd number, C is ±

1, ±

3, . . . , ±

(Q−

2), and when the Q is an even number, C is 0, ±

2, ±

4, . . . , ±

(Q−

2), and

the first digital code DA is selected from Q digital codes, and the first digital code DA is 0, ±

1, ±

2, . . . , ±

(Q−

1)/2 when the Q is an odd number, and the first digital code DA is ±

½

, ±

3/2, . . . , ±

(Q−

3)/2 when the Q is an even number.

15. The analog-digital converter according to claim 13, wherein

the analog operation circuit in said analog-digital conversion cell at the subsequent stage includes two or more capacitances for sampling the analog input signal VI and one operational amplifier, and when outputting the analog output signal VO, at least the one or more capacitances out of the capacitances is/are connected to an output of the operational amplifier and the other capacitance/capacitances is/are connected to a voltage in accordance with the first digital code DA.

16. The analog-digital converter according to claim 8, wherein

said second logic operation circuit operates a digital output signal that is an analog-digital conversion result based on the second digital code that each of said analog-digital conversion cells outputs, and when the digital output signal is a value larger than a maximum value of a code capable of an AD conversion, said second logic operation circuit outputs the maximum value as the digital output signal, and when the digital output signal is a value smaller than a minimum value of a code capable of an AD conversion, said second logic operation circuit outputs the minimum value as the digital output signal.

17. An analog-digital converter being an analog-digital converter that includes one or more analog-digital conversion cells and uses at least the one or more analog-digital conversion cells two times or more while converting an analog signal into a digital signal output, the analog-digital converter comprising:

a second logic operation circuit outputting a digital output signal that is an analog-digital conversion result based on a second digital code output by each conversion operation in the analog-digital conversion cell, and wherein

the analog-digital conversion cell performs an operation of the analog-digital conversion cell according to claim 1 at least once or more.

18. The analog-digital converter according to claim 17, wherein

at an initial use of the analog-digital conversion cell, the operation of the analog-digital conversion cell according to claim 1 is performed.