Ultra wideband baseband chip with intelligent array radio and method of use thereof
First Claim
Patent Images
1. A receiver, comprising:
- a plurality of channels for receiving a signal, wherein each channel receives the signal independently, each channel having an analog-to-digital converter for an in phase (I) signal of the received signal and an analog-to-digital converter for a quadrature (Q) signal of the received signal;
each channel further having a signal processing block coupled to the I and Q analog-to-digital converters; and
a data combiner coupled to the signal processing blocks of each channel, that combines the I signals from each channel and combines the Q signals from each channelwherein the signal processing blocks are further coupled to a controller, the controller comprising a combiner that combines incoming correlation values from the plurality of channelswherein the controller further includes a master symbol sync, a master frame sync coupled to the master symbol sync, and a master sampling frequency offset feedback control coupled to the master frame sync;
wherein the master symbol sync process incoming symbol synchronization correlations values from the plurality of channels to produce symbol boundary and packet detection control information;
wherein the master frame sync determines a start of channel estimation symbols, header symbols and data symbols with a received packet;
wherein the master sampling frequency offset feedback control provides control information to a symbol sync of the signal processing block and a phase locked loop that drives a clock using sampling frequency offset estimates from each channel.
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Abstract
An ultra wideband receiver, based on multiband orthogonal frequency division multiplexing (MB-OFDM), combines digital data from multiple channels after signal processing and before decoding. The receiver provides a master controller that synthesizes packet synchronization, frame synchronization, and sampling frequency offset information from multiple channels into signals that simultaneously control all channels of the receiver.
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Citations
17 Claims
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1. A receiver, comprising:
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a plurality of channels for receiving a signal, wherein each channel receives the signal independently, each channel having an analog-to-digital converter for an in phase (I) signal of the received signal and an analog-to-digital converter for a quadrature (Q) signal of the received signal; each channel further having a signal processing block coupled to the I and Q analog-to-digital converters; and a data combiner coupled to the signal processing blocks of each channel, that combines the I signals from each channel and combines the Q signals from each channel wherein the signal processing blocks are further coupled to a controller, the controller comprising a combiner that combines incoming correlation values from the plurality of channels wherein the controller further includes a master symbol sync, a master frame sync coupled to the master symbol sync, and a master sampling frequency offset feedback control coupled to the master frame sync; wherein the master symbol sync process incoming symbol synchronization correlations values from the plurality of channels to produce symbol boundary and packet detection control information; wherein the master frame sync determines a start of channel estimation symbols, header symbols and data symbols with a received packet; wherein the master sampling frequency offset feedback control provides control information to a symbol sync of the signal processing block and a phase locked loop that drives a clock using sampling frequency offset estimates from each channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method, comprising:
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receiving a signal; for a plurality of channels, each of which receives the signal independently, converting from analog to digital an in-phase (I) signal of the received signal and a quadrature (Q) signal of the received signal; signal processing each converted signal; and after the processing, combining the I signals from each channel and combining the Q signals from each channel; combining, by a combiner in a controller, incoming correlation values from the plurality of channels; processing, by the controller, incoming symbol synchronization correlations values from the plurality of channels to produce symbol boundary and packet detection control information; determining, by the controller, a start of channel estimation symbols, header symbols and data symbols with a received packet; and providing, by the controller, control information for the signal processing and to a phase locked loop that drives a clock using sampling frequency offset estimates from each channel. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification