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Software entity for the creation of a hybrid cycle simulation model

  • US 7,987,086 B2
  • Filed: 10/10/2008
  • Issued: 07/26/2011
  • Est. Priority Date: 09/12/2005
  • Status: Expired due to Fees
First Claim
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1. A software entity embodied in non-transitory tangible media for use with a digital design simulation model, comprising:

  • linkages for standard logic elements for abstracting one or more design interface components out of a cycle simulation environment constructed with a cycle stimulation model in which all design source components are compiled into 1-Cycle CDUs, all design source components are compiled into 2-Cycle CDUs, or design source components are compiled into a combination of 1-Cycle and 2-Cycle CDUs , andwherein is included a merge and build step wherein said combination of 1-Cycle and 2-Cycle CDUs are incorporated into a flattened cycle simulation model comprised of internal data structures representing low level primitive blocks thereby producing a cycle simulation model containing a mixture of 1-Cycle and 2-Cycle CDU representation of design component source,design interface emulation of interface which;

    (a) interacts with a hybrid cycle simulation model through the use of an API to extract the present value of the signals at the driving side of an interface, and(b) sets facilities within said hybrid cycle simulation model on the receiving side of the interface, andwherein said software entity'"'"'s control data and control code consists of information about delays, the mode that determines what facility accesses and alterations should be performed by the software entity, and a description of which bits of which wires and registers should be connected via an Application Program Interface for manipulating and accessing data pointers which represent a plurality of driver registers, receiver registers and bus interfaces, and further provides one propagation delay to the first part of a data transfer corresponding to a first clock edge and a same or different propagation delay to a second part of a data transfer corresponding to a second clock edge for use in a double data rate interface.

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