Method and apparatus for analyzing circuit model by reduction and computer program product for analyzing the circuit model

• US 7,987,439 B2
• Filed: 02/07/2008
• Issued: 07/26/2011
• Est. Priority Date: 02/27/2007
• Status: Expired due to Fees

• Current Assignee: Postech Academy-Industry Foundation
• Original Assignee: Postech Academy-Industry Foundation
• Inventors: Che, Hong Bo, Kim, Young Hwan
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US12/027,732
• Publication Number:
  US 20080209366A1
• Time in Patent Office: 1,265 Days
• Field of Search: None
• US Class Current: 716/103
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Provided are a method and apparatus for analyzing a circuit model by reducing, and a computer program product for analyzing the circuit model. The circuit model at least includes independent current source models, resistance models, and capacitance models. Also, the circuit model forms a resistance capacitance (RC) network with independent current sources. The method includes selecting a node to be removed using resistance information and comparing conductance of a capacitor for a given time step and the total conductance of the node. Further, the method includes removing the selected nodes and generating RC elements and independent current sources using adjacent nodes, which maintain the accuracy of node voltages of a circuit reduced in an accuracy order used for entrywise perturbation of the corresponding circuit equation. Moreover, an efficient method of handling the independent current sources while reducing the circuit is provided.

Claims

1. A method of analyzing a circuit model by reduction, through an apparatus comprising:

a memory, and a processor for executing instructions stored in the memory, the method comprising;

inputting information about the circuit model, the information comprising a circuit net list with independent current sources and a node state information of each of a plurality of nodes in the circuit model;

processing the circuit net list with the independent current sources for controlling an error and increasing a reduction ratio;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

processing a reduced circuit net list by the processor from data of the reduced circuit which is stored in the memory.

2. The method of claim 1, wherein the selecting of nodes comprises sorting the nodes in order of degree of the nodes.

3. The method of claim 1, wherein the selecting of nodes comprises determining whether a node is to be removed by comparing a conductance of a capacitor of the node and a sum of conductance of the nodes.

4. The method of claim 1, wherein the removing of the selected node comprises creating a resistor between each two nodes adjacent to the removed node.

5. The method of claim 1, wherein the removing of the selected node comprises creating grounded capacitor at each node adjacent to the removed node.

6. The method of claim 1, wherein the removing of the selected node comprises creating one of the independent current sources at each node adjacent to the removed node.

7. The method of claim 6, wherein the creating of the independent current sources comprises processing a symbolic name and a current scaling factor value of a piecewise linear (PWL) current source while generating the reduced circuit.

8. The method of claim 7, wherein processing the post reduced circuit net list comprises generating the PWL current source using the symbolic name and the current scaling factor value after generating the reduced circuit.

9. A method of analyzing a circuit model by reduction, through an apparatus comprising:

a memory; and

a processor for executing instructions stored in the memory, the method comprising;

inputting information about the circuit model, the information comprising a circuit net list with independent current sources and a node state information of each of a plurality of nodes in the circuit model;

processing the circuit net list with the independent current sources for controlling an error and increasing reduction ratio;

inputting an RC net list with independent current sources and node state information;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

processing a reduced circuit net list by the processor from data of the reduced circuit which is stored in the memory.

10. A method of analyzing a circuit model by reduction, through an apparatus comprising:

a memory; and

a processor for executing instructions stored in the memory, the method comprising;

inputting information about the circuit model, the information comprising a circuit net list with independent current sources and a node state information of each of a plurality of nodes in the circuit model;

processing the circuit net list with the independent current sources for controlling an error and increasing reduction ratio;

calculating an effective conductance of a capacitor for a given time step;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

processing a reduced circuit net list by the processor from data of the reduced circuit which is stored in the memory.

11. A method of analyzing a circuit model by reduction, through an apparatus comprising:

a memory; and

a processor for executing instructions stored in the memory, the method comprising;

inputting information about the circuit model, the information comprising a circuit net list with independent current sources and a node state information of each of a plurality of nodes in the circuit model;

processing the circuit net list with the independent current sources for controlling an error and increasing a reduction ratio;

calculating a conductance of a node in the circuit;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

processing a reduced circuit net list by the processor from data of the reduced circuit which is stored in the memory.

12. A non-transitory computer-readable medium having recorded thereon instructions executed by processing, through an apparatus comprising:

a memory; and

a processor for executing instructions stored in the memory, the instructions for inputting information about the circuit model, the information comprising a circuit net list with independent current sources and a node state information of each of a plurality of nodes in the circuit model;

processing the circuit net list with independent current sources for controlling an error and increasing reduction ratio;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

processing a reduced circuit net list by the processor from data of the reduced circuit which is stored in the memory.

13. A computer program product for performing a circuit simulation by realizing a reduced circuit of a power distribution network for simulating the power distribution network, the computer program product embodied on a non-transitory computer-readable medium and comprising instructions, through an apparatus comprising:

a memory; and

a processor for executing instructions stored in the memory, the instructions for;

inputting information about the circuit model, the information comprising a circuit net list with independent current sources and a node state information of each of a plurality of nodes in the circuit model;

processing the circuit net list with the independent current sources for controlling an error and increasing reduction ratio;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

processing a reduced circuit net list by the processor from data of the reduced circuit which is stored in the memory.

14. An apparatus for analyzing a circuit model by reduction, the apparatus comprising:

a processor;

a memory; and

instructions stored in the memory and executed by the processor, for;

inputting information about the circuit model, the information comprising a circuit net list with independent current sources and a node state information of each of a plurality of nodes in the circuit;

processing the circuit net list with the independent current sources for controlling an error and increasing reduction ratio;

selecting one of the nodes to be removed;

removing the selected node and generating a reduced circuit; and

processing a reduced circuit net list by the processor from data of the reduced circuit which is stored in the memory.