Photo-masking method for fabricating TFT array substrate

• US 7,989,142 B2
• Filed: 03/19/2007
• Issued: 08/02/2011
• Est. Priority Date: 03/17/2006
• Status: Active Grant

• Current Assignee: InnoLux Corporation
• Original Assignee: InnoLux Corporation
• Inventors: Fu, Jian-Jhong
• Primary Examiner(s): Chacko-Davis; Daborah
• Application Number:
  US11/725,700
• Publication Number:
  US 20070218581A1
• Time in Patent Office: 1,597 Days
• Field of Search: None
• US Class Current: 430/311
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

An exemplary method for fabricating a TFT array substrate includes providing an insulating substrate (201); coating a gate metal layer (202) on the substrate; forming a plurality of gate electrodes (212) using a first photo-mask process; forming a gate insulating layer (203), a semiconducting layer (205), and a source/drain metal layer (206) on the substrate having the gate electrodes; forming a plurality of source electrodes (217) and a plurality of drain electrodes (218) using a second photo-mask process; forming a passivation material layer (209) and a photo resist layer on the gate insulating layer, the source electrodes and the drain electrodes; forming a passivation layer (219) and the photo resist pattern (234) using a third photo-mask process; forming a transparent conductive metal layer (204) on the photo resist pattern, the drain electrode and the gate insulating layer; and forming a pixel electrode (214) through removing the photo resist pattern.

Claims

1. A method for fabricating a thin film transistor (TFT) array substrate, the method comprising:

providing an insulating substrate;

coating a gate metal layer on the substrate;

forming a plurality of gate electrodes using a first photo-mask process;

forming a gate insulating layer, a semiconducting layer, and a source/drain metal layer on the substrate having the gate electrodes;

forming a plurality of source electrodes and a plurality of drain electrodes using a second photo-mask process, each of pairs of one source electrode and one drain electrode defining a channel therebetween;

forming a passivation layer and a photo-resist layer on the gate insulating layer, the source electrodes and the drain electrodes;

exposing the photo-resist layer using a third photo-mask process, thereby forming a photo-resist pattern, the photo-resist pattern exposing portions of the passivation layer, wherein each exposed portion of the passivation layer is above both a respective drain electrode and a portion of the gate insulating layer adjacent to the drain electrode;

etching away the exposed portions of the passivation layer, thereby forming a patterned passivation layer, the patterned passivation layer being on the semiconducting layer, the gate insulating layer and the source electrodes and leaving the drain electrodes and the portions of the gate insulating layer exposed;

forming a transparent conductive metal layer on the photo-resist pattern, the drain electrodes and the gate insulating layer; and

forming a plurality of pixel electrodes through removing the photo-resist pattern and the transparent conductive metal layer on the photo-resist pattern.

2. The method as claimed in claim 1, wherein the second photo-mask process comprises coating another photo-resist layer on the source/drain metal layer, exposing the another photo-resist layer of the second photo-mask process using a photo-mask having a plurality of slits, and developing the exposed another photo-resist layer of the second photo-mask process to form another photo-resist pattern.

3. The method as claimed in claim 2, wherein the another photo-resist pattern of the second photo-mask process has a plurality of grooves.

4. The method as claimed in claim 2, wherein the second photo-mask process further comprises etching the another photo-resist layer of the second photo-mask process beneath the grooves, thereby exposing a portion of the source/drain metal layer corresponding to each groove.

5. The method as claimed in claim 2, wherein the second photo-mask process further comprises etching the source/drain metal layer and the semiconducting layer, thereby forming a source/drain metal layer pattern and a semiconducting layer pattern.

6. The method as claimed in claim 1, wherein the second photo-mask process further comprises depositing another photo-resist layer and utilizes a light diffraction technique to expose and develop the another photo-resist layer of the second photo-mask process.

7. The method as claimed in claim 1, wherein the second photo-mask process further comprises depositing another photo-resist layer and utilizes a photo-mask having transparent portions, opaque portions and semitransparent portions to expose the another photo-resist layer of the second photo-mask process to produce another photo-resist pattern having a plurality of grooves.

8. The method as claimed in claim 1, wherein the first photo-mask process comprises depositing another photo-resist layer on the gate metal layer and exposing the another photo-resist layer of the first photo-mask process by a photo-mask.

9. The method as claimed in claim 8, wherein the first photo-mask process further comprises etching the gate metal layer and removing residual portions of the another photo-resist layer of the first photo-mask process.

10. The method as claimed in claim 1, wherein the process of forming a plurality of gate electrodes further comprises forming a plurality of common lines at the same time.

11. The method as claimed in claim 1, wherein the substrate is made from glass or quartz.

12. The method as claimed in claim 1, wherein the transparent conductive layer is made from indium tin oxide or indium zinc oxide.

13. The method as claimed in claim 1, wherein the gate metal layer is made from material including any one or more items selected from the group consisting of aluminum, molybdenum, copper, chromium, and tantalum.

14. The method as claimed in claim 1, wherein the source/drain metal layer is made from material including any one or more items selected from the group consisting of aluminum, aluminum alloy, molybdenum, tantalum, and molybdenum-tungsten alloy.

15. A method for fabricating a thin film transistor (TFT) array substrate, the method comprising:

providing an insulating substrate;

coating a gate metal layer and a first photo-resist layer on the substrate;

exposing the first photo-resist layer using a first photo-mask process, thereby forming a first photo-resist pattern;

using the first photo-resist pattern as a mask, and etching the gate metal layer, thereby forming a plurality of gate electrodes;

forming a gate insulating layer, a semiconducting layer, and a source/drain metal layer on the substrate having the gate electrodes;

coating a second photo-resist layer on the source/drain metal layer;

exposing the second photo-resist layer using a second photo-mask process, thereby forming a plurality of second photo-resist patterns, wherein each second photo-resist pattern has a groove, and a thickness of the second photo-resist pattern beneath the groove is less than a thickness of other portions of the second photo-resist pattern;

using the plurality of second photo-resist patterns as a mask, and etching portions of the gate insulating layer, the semiconducting layer and the source/drain metal layer not covered by the plurality of second photo-resist patterns, thereby forming a source/drain metal layer pattern;

etching each second photo-resist pattern beneath the groove, thereby exposing the source/drain metal layer pattern corresponding to the grooves;

etching the source/drain metal layer and a part of the semiconducting layer pattern beneath the grooves, thereby forming a plurality of source electrodes, a plurality of drain electrodes, and a plurality of channels, each channel defined between a respective pair of one source electrode and one drain electrode;

forming a passivation layer and a third photo-resist layer on the gate insulating layer, the source electrodes and the drain electrodes;

exposing the third photo-resist layer using a third photo-mask process, thereby forming a third photo-resist pattern, the third photoresist pattern exposing portions of the passivation layer, wherein each exposed portion of the passivation layer is above both a respective drain electrode and a portion of the gate insulating layer adjacent to the drain electrode;

etching away the exposed portions of the passivation layer, thereby forming a patterned passivation layer, the patterned passivation layer being on the semiconducting layer, the gate insulating layer and the source electrodes and leaving the drain electrodes and the portions of the gate insulating layer exposed;

forming a transparent conductive metal layer on the third photo-resist pattern, the drain electrodes and the gate insulating layer; and

forming a plurality of pixel electrodes through removing the third photo-resist pattern and the transparent conductive metal layer on the third photo-resist pattern.