Anisotropic stress generation by stress-generating liners having a sublithographic width
First Claim
1. A method of forming a semiconductor structure comprising:
- forming a semiconductor device structure on a semiconductor substrate, wherein said semiconductor device structure includes a gate line of a field effect transistor, wherein said gate line has a linear edge protruding above said semiconductor substrate;
forming a stress-generating layer comprising a stress-generating material on said semiconductor device structure; and
patterning said stress-generating layer into a plurality of linear stress-generating stripes, each having lengthwise edges that are parallel to said linear edge and laterally spaced from one another and overlying a source region and a drain region of said field effect transistor.
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Accused Products
Abstract
A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.
16 Citations
10 Claims
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1. A method of forming a semiconductor structure comprising:
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forming a semiconductor device structure on a semiconductor substrate, wherein said semiconductor device structure includes a gate line of a field effect transistor, wherein said gate line has a linear edge protruding above said semiconductor substrate; forming a stress-generating layer comprising a stress-generating material on said semiconductor device structure; and patterning said stress-generating layer into a plurality of linear stress-generating stripes, each having lengthwise edges that are parallel to said linear edge and laterally spaced from one another and overlying a source region and a drain region of said field effect transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification