Anisotropic stress generation by stress-generating liners having a sublithographic width

• US 7,989,291 B2
• Filed: 02/25/2010
• Issued: 08/02/2011
• Est. Priority Date: 01/22/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Clevenger, Lawrence A., Purushothaman, Sampath, Doris, Bruce B., Radens, Carl J., Huang, Elbert E.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/712,369
• Publication Number:
  US 20100151638A1
• Time in Patent Office: 523 Days
• Field of Search: 438/142, 438/197, 438/262, 438/694, 438/704, 438/775, 438/780
• US Class Current: 438/262
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.

Claims

1. A method of forming a semiconductor structure comprising:

forming a semiconductor device structure on a semiconductor substrate, wherein said semiconductor device structure includes a gate line of a field effect transistor, wherein said gate line has a linear edge protruding above said semiconductor substrate;

forming a stress-generating layer comprising a stress-generating material on said semiconductor device structure; and

patterning said stress-generating layer into a plurality of linear stress-generating stripes, each having lengthwise edges that are parallel to said linear edge and laterally spaced from one another and overlying a source region and a drain region of said field effect transistor.

2. The method of claim 1, wherein said plurality of said linear stress-generating stripes applies a substantially uniaxial stress to said semiconductor device structure in a direction that is parallel to said linear edge.

3. The method of claim 1, further comprising:

applying a non-photosensitive self-assembling block copolymer layer comprising a first polymeric block component and second polymeric block component on a substrate;

forming a plurality of polymeric stripes comprising said first polymeric block component and having a sublithographic width by removing polymeric stripes comprising said second polymeric block component; and

transferring a pattern present within said plurality of said polymeric stripes into said stress-generating layer by an etch, whereby remaining portions of said stress-generating layer after said etch form said plurality of said linear stress-generating stripes.

4. The method of claim 3, wherein each of said plurality of said linear stress-generating stripes has a sublithographic width, wherein said width is measured in a direction perpendicular to one of said lengthwise edges.

5. The method of claim 3, further comprising:

forming a matrix of said second polymeric block component laterally abutting and surrounding each of said plurality of said polymeric stripes; and

removing said matrix selective to said plurality of said polymeric stripes.

6. The method of claim 1, wherein a lengthwise dimension of each of said plurality of said linear stress-generating stripes is lithographic, and wherein a spacing between an adjacent pair of said plurality of said linear stress-generating stripes is sublithographic.

7. The method of claim 1, wherein said plurality of said linear stress-generating stripes applies a substantially uniaxial stress to a channel of said field effect transistor in a direction that is parallel to a lengthwise edge of said gate conductor line.

8. The method of claim 7, further comprising:

forming another field effect transistor on said semiconductor substrate, wherein said another field effect transistor includes another gate line, another source side metal semiconductor alloy region, and another drain side metal semiconductor alloy region,

wherein said stress-generating layer abuts said another gate line, said another source side metal semiconductor alloy region, and said another drain side metal semiconductor alloy region upon formation, wherein said stress-generating layer applies a longitudinal stress and a transverse stress to a channel of said another field effect transistor.

9. The method of claim 8, further comprising forming another field effect transistor located on said semiconductor substrate and not directly contacting any structure comprising said stress-generating material.

10. The method of claim 1, wherein said plurality of linear stress-generating stripes does not overlie any top surface of said gate line.