Trench device structure and fabrication

• US 7,989,293 B2
• Filed: 02/24/2009
• Issued: 08/02/2011
• Est. Priority Date: 02/24/2009
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A., Zeng, Jun
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US12/391,450
• Publication Number:
  US 20100214016A1
• Time in Patent Office: 889 Days
• Field of Search: 438/197, 438/206, 438/207, 438/270, 438/271, 257/E21.149, 257/E21.468
• US Class Current: 438/270
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertical-current-flow device includes a trench which includes an insulated gate and which extends down into first-conductivity-type semiconductor material. A phosphosilicate glass layer is positioned above the insulated gate and a polysilicon layer is positioned above the polysilicate glass layer. Source and body diffusions of opposite conductivity types are positioned adjacent to a sidewall of the trench. A drift region is positioned to receive majority carriers which have been injected by the source, and which have passed through the body diffusion. A drain region is positioned to receive majority carriers which have passed through the drift region. The gate is capacitively coupled to control inversion of a portion of the body region. As an alternative, a dielectric layer may be used in place of the doped glass where permanent charge is positioned in the dielectric layer.

Claims

1. A vertical-current-flow device, comprising:

a trench, extending into a semiconductor material, including an insulated gate;

a dielectric layer, which contains a dopant of a first conductivity type for said semiconductor material, above said insulated gate;

source and body diffusions of first and second respective conductivity types in said semiconductor material, adjacent to at least one sidewall of said trench;

a drift region in said semiconductor material, positioned to receive majority carriers which have been injected by said source, and which have passed through said body diffusion;

a drain region of said first conductivity type in said semiconductor material, positioned to receive majority carriers which have passed through said drift region;

a lightly doped diffusion of said first conductivity type, in said semiconductor material, adjacent said dielectric layer; and

a layer of doped polysilicon above said dielectric layer.

2. The vertical-current-flow device of claim 1, wherein said insulated gate is a split gate.

3. The vertical-current-flow device of claim 2, wherein said insulated gate includes a polysilicon layer.

4. The vertical-current flow device of claim 1, further comprising permanent charge in said dielectric layer.

5. A method of operating a vertical-current-flow semiconductor device, comprising the actions of:

using an insulated gate in a trench to control inversion of a body diffusion in a semiconductor material, said trench including a glass layer and a doped polysilicon layer;

in a drift region in said semiconductor material, receiving majority carriers which have been injected by a first-conductivity-type source, and which have passed through said body diffusion and through a lightly doped first-conductivity-type region which is self-aligned to said glass layer; and

in a first-conductivity-type drain region in said semiconductor material, receiving majority carriers which have passed through said drift region;

wherein said body region has a second conductivity type, and said gate is capacitively coupled to control inversion of a portion of said body region;

and wherein said glass layer contains a species which is a first-conductivity-type dopant for said semiconductor material;

and wherein said doped polysilicon layer also contains a species which is a first-conductivity-type dopant for said semiconductor material.

6. The method of claim 5, wherein said majority carriers are electrons.

7. The method of claim 5, further comprising a lightly doped diffusion between said source and said body diffusion.

8. The method of claim 5, wherein said insulated gate is a split gate.

9. The method of claim 5, further comprising permanent charge in said glass layer.

10. The method of claim 8 wherein said split gate includes a polysilicon layer.

11. The method of claim 5, wherein said first-conductivity-type dopant is an n-type dopant.

12. The method of claim 5, wherein said second conductivity type is p-type.

13. The method of claim 12, wherein said n-type dopant is phosphorus, arsenic or antimony.