Semiconductor device packages with electromagnetic interference shielding

• US 7,989,928 B2
• Filed: 06/22/2009
• Issued: 08/02/2011
• Est. Priority Date: 02/05/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Liao, Kuo-Hsien, Hung, Chih-Pin, Chiu, Chi-Tsung
• Primary Examiner(s): Lee; Eugene
• Assistant Examiner(s): Gumedzoe; Peniel M
• Application Number:
  US12/489,115
• Publication Number:
  US 20090256244A1
• Time in Patent Office: 771 Days
• Field of Search: 257/659, 257/660, 257/E23.114, 257/708, 257/728, 361/841, 361/816, 294/12, 298/41, 298/45, 298/52
• US Class Current: 257/659
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49153 : with shaping or forcing terminal into base aperture
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49789 : Obtaining plural product pieces from unitary workpiece

Abstract

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Claims

1. A semiconductor device package, comprising:

a substrate unit including

an upper surface,

a lower surface,

a lateral surface disposed adjacent to a periphery of the substrate unit and fully extending between the upper surface and the lower surface of the substrate unit, the lateral surface of the substrate unit being substantially planar, and

a grounding element disposed adjacent to the periphery of the substrate unit, the grounding element corresponding to a remnant of an internal grounding via and including a connection surface that is electrically exposed adjacent to the lateral surface of the substrate unit;

a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit;

a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including exterior surfaces that include a lateral surface, the lateral surface of the package body being substantially aligned with the lateral surface of the substrate unit; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the connection surface of the grounding element,

wherein the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the electromagnetic interference shield and partially extends between the upper surface and the lower surface of the substrate unit, such that a height of the grounding element is less than a thickness of the substrate unit.

2. The semiconductor device package of claim 1, wherein the substrate unit includes a pair of internal grounding layers, and the grounding element extends between the pair of internal grounding layers.

3. The semiconductor device package of claim 2, wherein the pair of internal grounding layers are disposed between the upper surface and the lower surface of the substrate unit.

4. The semiconductor device package of claim 1, wherein a height of the grounding element is in the range of 0.1 mm to 1.6 mm, and a width of the grounding element is in the range of 75 μ

m to 275 μ

m.

5. The semiconductor device package of claim 1, wherein the electromagnetic interference shield includes a lateral portion that extends along the lateral surface of the substrate unit.

6. The semiconductor device package of claim 5, wherein a lower end of the lateral portion is substantially aligned with the lower surface of the substrate unit.

18. The semiconductor device package of claim 1, wherein the lateral surface of the package body is substantially co-planar with the lateral surface of the substrate unit.

7. A semiconductor device package, comprising:

a substrate unit including

a first surface,

a second opposing surface,

an electrically conductive layer disposed between the first surface and the second opposing surface of the substrate unit, and

a grounding element extending between the electrically conductive layer and the second opposing surface of the substrate unit, the grounding element including a first end, a second end, and a lateral surface, the first end disposed between the first surface and the second opposing surface of the substrate unit and being spaced apart from the first surface of the substrate unit, the second end disposed adjacent to the second opposing surface of the substrate unit, the lateral surface disposed adjacent to a periphery of the substrate unit;

a semiconductor device disposed adjacent to the first surface of the substrate unit and electrically connected to the substrate unit;

a package body disposed adjacent to the first surface of the substrate unit and covering the semiconductor device, the package body including exterior surfaces; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the lateral surface of the grounding element,

wherein the grounding element includes a first via pad remnant, a second via pad remnant, and a plated channel remnant extending between the first via pad remnant and the second via pad remnant,

wherein the first via pad remnant is disposed adjacent to the electrically conductive layer of the substrate unit, and the second via pad remnant is disposed adjacent to the second opposing surface of the substrate unit.

12. The semiconductor device package of claim 7, wherein the substrate unit further includes a lateral surface fully extending between the first surface and the second opposing surface of the substrate unit, the lateral surface of the substrate unit is substantially planar and is substantially orthogonal with respect to the second opposing surface of the substrate unit, and the lateral surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit.

13. The semiconductor device package of claim 12, wherein the exterior surfaces of the package body include a lateral surface, and the lateral surface of the package body is substantially co-planar with the lateral surface of the substrate unit.

14. The semiconductor device package of claim 7, wherein the semiconductor device is wire bonded to the substrate unit.

15. The semiconductor device package of claim 7, further comprising a passive semiconductor device surface mounted to the substrate unit.

16. The semiconductor device package of claim 7, wherein the electromagnetic interference shield is a conformal shield that includes a first layer and a second layer disposed adjacent to the first layer, and the first layer and the second layer include different electrically conductive materials.

8. A method of forming a semiconductor device package, comprising:

providing a substrate including an upper surface, a lower surface, and grounding vias partially extending between the upper surface and the lower surface of the substrate, such that a height of each of the grounding vias is less than a thickness of the substrate;

electrically connecting a semiconductor device to the upper surface of the substrate;

applying a molding material to the upper surface of the substrate to form a molded structure covering the semiconductor device;

forming cutting slits fully extending through the molded structure and the substrate, the cutting slits being aligned with the substrate, such that;

(a) the substrate is sub-divided to form a separated substrate unit;

(b) the molded structure is sub-divided to form a separated package body disposed adjacent to the substrate unit, the package body including exterior surfaces; and

(c) remnants of the grounding vias correspond to grounding elements disposed adjacent to a periphery of the substrate unit, each of the grounding elements including an exposed connection surface; and

subsequent to forming the cutting slits, applying an electromagnetic interference coating to the exterior surfaces of the package body and the connection surfaces of the grounding elements to form an electromagnetic interference shield.

9. The method of claim 8, further comprising securing the lower surface of the substrate to a tape, and wherein forming the cutting slits is such that the cutting slits extend partially through the tape.

10. The method of claim 8, wherein the substrate unit includes a lateral surface, the exterior surfaces of the package body include a lateral surface, and forming the cutting slits is such that the lateral surface of the package body is substantially aligned with the lateral surface of the substrate unit.

11. The method of claim 8, wherein a width of at least one of the cutting slits is in the range of 100 μ

m to 600 μ

m.

17. The method of claim 8, wherein the electromagnetic interference shield includes a lateral portion, and the lateral portion has a lower end that is substantially co-planar with a lower surface of the substrate unit.