Method of forming stacked-die integrated circuit

• US 7,989,959 B1
• Filed: 01/29/2009
• Issued: 08/02/2011
• Est. Priority Date: 01/29/2009
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Rahman, Arifur
• Primary Examiner(s): Parekh; Nitin
• Application Number:
  US12/361,827
• Time in Patent Office: 915 Days
• Field of Search: 257/777, 257/686, 257/774, 257/E23.145, 438/108, 438/109
• US Class Current: 257/777
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06132 being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/06519 including bonding areas providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/14132 being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/14135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/14136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/14177 Combinations of arrays with different layouts
• CPC Class Codes: H01L 2224/14515 Bump connectors having different functions
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A stacked-die integrated circuit and a method of fabricating same. The stacked-die integrated circuit has circuitry formed in the first surface of a mother die, a plurality of through-die vias with at least one through-die via providing electrical connection between the circuitry of the mother die and the second surface and a plurality of contact pads formed in the second surface of the semiconductor die for mounting a daughter die wherein some of the contact pads are electrically isolated dummy pads.

Claims

1. An integrated circuit device, comprising:

a first die having circuitry formed in a first surface;

a plurality of through-die vias formed in the first die, at least one through-die via of the plurality of through-die vias providing electrical connection between the circuitry of the first die and a second surface of the first die;

a first plurality of contact pads formed in the second surface of the first die; and

a second die mounted on the first die, the second die having circuitry and a second plurality of contact pads that are soldered to corresponding ones of the first plurality of contact pads;

wherein first contact pads of the first plurality of contact pads and the corresponding contact pads of the second plurality of contact pads provide electrical connection between the circuitry of the first die and the circuitry of the second die by means of a through-die via; and

wherein second contact pads of the first plurality of contact pads and the corresponding contact pads of the second plurality of contact pads are electrically isolated from the circuitry of the first die and electrically isolated from the circuitry of the second die.

2. The integrated circuit device of claim 1 wherein the second contact pads of the first plurality of contact pads are formed with the same pitch and height as the first contact pads of the first plurality of contact pads.

3. The integrated circuit device of claim 1 wherein the of the first plurality of contact pads contact pads of the first plurality of contact pads are formed with a finer pitch than the first contact pads of the first plurality of contact pads.

4. The integrated circuit device of claim 3 wherein the pitch of the first plurality of contact pads and the pitch of the second plurality of contact pads are is enabled to accommodate capillary flow of an under fill material.

5. An integrated circuit device, comprising:

a semiconductor mother die comprising circuitry formed in a first surface and a first plurality of contact pads formed in a second surface, at least one of the first plurality of contact pads being electrically connected to the circuitry by means of a through-die via and at least one of the first plurality of contact pads being electrically isolated from the circuitry;

a daughter die mounted to the mother die and comprising circuitry and a second plurality of contact pads;

an array of solder bumps bonding the second plurality of contact pads of the daughter die to the corresponding contact pads of the first plurality of contact pads of the mother die;

wherein the at least one contact pad of the first plurality of contact pads that is electrically isolated from the circuitry of the mother die and the corresponding contact pad of the second plurality of contact pads is electrically isolated from the circuitry of the mother die and electrically isolated from the circuitry of the daughter die.

6. The integrated circuit device of claim 5, further comprising under fill material disposed in spaces between the mother die and the daughter die.

7. The integrated circuit device of claim 5 wherein the at least one contact pad of the first plurality of contact pads that is electrically isolated from the circuitry of the mother die is connected to a blind through-die via.

8. The integrated circuit device of claim 5 further comprising a packaging substrate mounted to contact pads on the first surface of the mother die.

9. The integrated circuit device of claim 8 further comprising packaging material disposed to provide electrical insulation and mechanical protection for the electrically connected mother die, daughter die and packaging substrate.

10. A method of fabricating a stacked-die integrated circuit device, comprising:

forming a semiconductor mother die, wherein the mother die comprises circuitry and a first plurality of contact pads, at least one contact pad of the first plurality of contact pads being electrically connected to the circuitry by means of a through-die via and at least one contact pad of the first plurality of contact pads being electrically isolated from the circuitry of the mother die;

forming a semiconductor daughter die, wherein the daughter die comprises circuitry and a second plurality of contact pads; and

mounting the daughter die to the mother die with an array of solder bumps bonding the second plurality of contact pads of the daughter die to the corresponding contact pads of the first plurality of contact pads of the mother die such that the circuitry of the daughter die is electrically coupled to the circuitry of the mother die;

wherein the at least one contact pad of the first plurality of contact pads that is electrically isolated from the circuitry of the mother die and the corresponding contact pad of the second plurality of contact pads is electrically isolated from the circuitry of the mother die and electrically isolated from the circuitry of the daughter die.

11. The method of claim 10 wherein the mounting of the daughter die further results in the daughter die and the mother die being mechanically coupled to each other.

12. The method of claim 10 further comprising underfilling the daughter die with a thermosetting packaging material.

13. The method of claim 12 wherein the underfilling provides thermal and mechanical protection to the integrated circuit device.

14. The method of claim 10 wherein the daughter die is of a plurality of daughter dice, each daughter die of the plurality of daughter dice being mounted to the back surface of a mother die.

15. The method of claim 10 wherein the integrated circuit device is a field programmable gate array.