Semiconductor device

• US 7,989,960 B2
• Filed: 02/04/2009
• Issued: 08/02/2011
• Est. Priority Date: 02/08/2008
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Araki, Makoto, Shinohara, Minoru, Sugiyama, Michiaki
• Primary Examiner(s): Parekh; Nitin
• Application Number:
  US12/365,806
• Publication Number:
  US 20090200680A1
• Time in Patent Office: 909 Days
• Field of Search: 257/777, 257/686, 257/723, 257/784, 257/E23.169
• US Class Current: 257/777
• CPC Class Codes: G06F 1/185 Mounting of expansion boards
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/5388 : for flat cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Claims

1. A semiconductor device comprising:

a wiring board having a main surface and a rear surface and external connecting terminals formed on the rear surface;

a memory chip mounted on the main surface of the wiring board;

a controller chip mounted on the memory chip and controlling the memory chip; and

an interposer mounted on the memory chip and electrically connected to the controller chip,

wherein first terminals are formed on a first side of the memory chip,

the interposer is disposed between the first side of the memory chip and the controller chip,

second terminals are formed on a first side of the interposer, third terminals are formed on a second side perpendicular to the first side and fourth terminals are formed on a third side opposed to the first side,

the second terminals formed on the first side of the interposer are electrically connected to the first terminals formed on the first side of the memory chip,

the third terminals formed on the second side of the interposer are electrically connected to the external connecting terminals through fifth terminals provided on one side of the main surface of the wiring board, and

the fourth terminals formed on the third side of the interposer are electrically connected to the controller chip.

2. The semiconductor device according to claim 1,

wherein a plurality of the memory chips are mounted in a stacked manner on the main surface of the wiring board, and

the plurality of the memory chips are stacked in a dislocated manner in a direction perpendicular to the first side so that the first terminals provided on their first sides are exposed.

3. The semiconductor device according to claim 2,

wherein, of the plurality of the memory chips, the memory chip of a lowermost layer and the other memory chips are stacked in a state of being rotated 180°

from each other within the main surface of the wiring board so that their first sides on which the first terminals are formed are directed in opposite directions,

the first terminals of the memory chip of the lowermost layer are electrically connected to the interposer through wirings of the wiring board connected to the fifth terminals, and

the first terminals of the other memory chips are electrically connected to the second terminals of the interposer.

4. The semiconductor device according to claim 3,

wherein the controller chip is connected to the fourth terminals of the interposer through sixth terminals provided on a first side of the controller chip, and

lengths of the first and third sides of the interposer are closer to a length of the first side of the memory chip than a length of the first side of the controller chip.

5. A semiconductor device comprising:

a wiring board having a main surface and a rear surface and external connecting terminals formed on the rear surface;

a memory chip mounted on the main surface of the wiring board; and

a controller chip mounted on the memory chip,

wherein first terminals are formed on a first side of the memory chip,

second terminals are formed on a first side of the controller chip, and third terminals are formed on a second side perpendicular to the first side,

the second terminals formed on the first side of the controller chip are electrically connected to the first terminals formed on the first side of the memory chip,

the third terminals formed on the second side of the controller chip are electrically connected to the external connecting terminals through fourth terminals on the main surface of the wiring board provided on a side of a second side perpendicular to the first side of the memory chip,

a plurality of the memory chips are mounted in a stacked manner on the main surface of the wiring board,

the plurality of the memory chips are stacked in a dislocated manner in a direction perpendicular to the first side so that the respective first terminals provided on their first sides are exposed,

of the plurality of the memory chips, the memory chip of a lowermost layer and the other memory chips are stacked in a state of being rotated 180°

from each other within the main surface of the wiring board so that their first sides on which the respective first terminals are formed are directed in opposite directions,

the first terminals of the memory chip of the lowermost layer are electrically connected to the controller chip through wirings of the wiring board connected to the fourth terminals, and

the respective first terminals of the other memory chips are electrically connected to the second terminals of the controller chip.

6. A semiconductor device comprising:

a wiring board having a main surface and a rear surface and external connecting terminals formed on the rear surface;

a plurality of memory chips stacked on the main surface of the wiring board; and

a controller chip and an interposer mounted on a memory chip of an uppermost layer of the plurality of the stacked memory chips,

wherein each of the plurality of the memory chips has a first side and a second side intersecting the first side and the plurality of the memory chips are stacked in a dislocated manner so that a plurality of first terminals disposed along the first sides are exposed,

the plurality of first terminals and the controller chip are electrically connected through the interposer,

a plurality of second terminals electrically connected to the external connecting terminals are disposed along a side of the wiring board adjacent to the second side on the main surface of the wiring board,

a plurality of third terminals are disposed on a main surface of the interposer in a vicinity of the plurality of second terminals, and

the plurality of second terminals and the plurality of third terminals are connected with wires, thereby electrically connecting the interposer and the wiring board.

7. The semiconductor device according to claim 6,

wherein a plurality of fourth terminals electrically connected to the plurality of third terminals and the controller chip are disposed in a vicinity of the plurality of first terminals on the main surface of the interposer, and

the plurality of the respective first terminals and the plurality of fourth terminals are connected with wires, thereby electrically connecting the plurality of the memory chips and the interposer.

8. The semiconductor device according to claim 6,

wherein the controller chip is mounted on the interposer.

9. The semiconductor device according to claim 8,

wherein a plurality of fifth terminals are disposed on a main surface of the controller chip,

a plurality of sixth terminals electrically connected to the plurality of third terminals and the plurality of fourth terminals are disposed in a vicinity of the plurality of fifth terminals on the main surface of the interposer, and

the plurality of fifth terminals and the plurality of sixth terminals are connected with wires, thereby electrically connecting the controller chip and the interposer.

10. The semiconductor device according to claim 9,

wherein the plurality of fifth terminals are disposed along three sides of the main surface of the controller chip.

11. The semiconductor device according to claim 9,

wherein the plurality of fifth terminals are disposed along four sides of the main surface of the controller chip.

12. The semiconductor device according to claim 6,

wherein the interposer has a U-shape in its plan view,

the controller chip is mounted next to the interposer inside an area surrounded by the U-shape,

a plurality of fifth terminals are formed along three sides of a main surface of the controller chip, and

the controller chip and the interposer are electrically connected by connecting, with wires, the plurality of fifth terminals formed on the main surface of the controller chip and a plurality of sixth terminals which are included in a plurality of terminals formed on the interposer and disposed in a vicinity of the plurality of fifth terminals.

13. The semiconductor device according to claim 12,

wherein the U-shape of the interposer in its plan view is formed by mounting three interposers each having a rectangular planar shape next to each other on the memory chip of the uppermost layer of the memory stack.

14. The semiconductor device according to claim 6,

wherein the interposer has a hollow-square shape in its plan view in which an rectangular opening is formed,

the controller chip is mounted next to the interposer inside the rectangular opening,

a plurality of fifth terminals are formed along four sides of a main surface of the controller chip, and

the controller chip and the interposer are electrically connected by connecting, with wires, the plurality of fifth terminals formed on the main surface of the controller chip and a plurality of sixth terminals which are included in a plurality of terminals formed on the interposer and disposed in a vicinity of the plurality of fifth terminals.

15. The semiconductor device according to claim 14,

wherein the hollow-square shape of the interposer in its plan view is formed by mounting four interposers each having a rectangular planar shape next to each other on the memory chip of the uppermost layer.

16. The semiconductor device according to claim 6,

wherein each two of the controller chips and interposers are mounted on the memory chip of the uppermost layer.

17. The semiconductor device according to claim 6,

wherein external dimensions of the wiring board are the same as external dimensions of a wiring board of a micro secured digital (SD) card.