Driving circuit with impedence calibration

• US 7,990,178 B2
• Filed: 12/01/2009
• Issued: 08/02/2011
• Est. Priority Date: 12/01/2009
• Status: Active Grant

• Current Assignee: Himax Imaging, Inc. (Himax Technologies Incorporated)
• Original Assignee: Himax Imaging, Inc. (Himax Technologies Incorporated)
• Inventors: Liu, Chih-Min, Yin, Ping-Hung
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US12/628,226
• Publication Number:
  US 20110128036A1
• Time in Patent Office: 609 Days
• Field of Search: 326 82- 83, 326/86, 327108-109
• US Class Current: 326/83
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018571 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018585 programmable

Abstract

A driving circuit includes at least a driving unit. The driving circuit includes a first bias component, a second bias component, and four metal-oxide-semiconductor (MOS) transistors. The first bias component has a first node coupled to a first reference voltage and a second node for outputting a first bias current. The second bias component has a first node for draining a second bias current and a second node coupled to a second reference voltage different from the first reference voltage. Each of the MOS transistors has a control node for receiving one of input signal pairs, a node coupled to one of the bias components and another node coupled to one of the output ports of the driving circuit. The four MOS transistors are of a same conductive type.

Claims

1. A driving circuit, comprising:

a plurality of driving units each coupled between a first reference voltage and a second reference voltage, each driving unit comprising;

a first bias component, having a first node coupled to the first reference voltage, and a second node for outputting a first bias current;

a second bias component, having a first node for draining a second bias current, and a second node coupled to the second reference voltage different from the first reference voltage;

a first metal-oxide-semiconductor (MOS) transistor, having a control node for receiving a first input signal, a first connection node coupled to the second node of the first bias component, and a second connection node coupled to a first output port of the driving circuit;

a second MOS transistor, having a control node for receiving a second input signal, a first connection node coupled to the second node of the first bias component, and a second connection node coupled to a second output port of the driving circuit;

a third MOS transistor, having a control node for receiving the second input signal, a first connection node coupled to the first output port of the driving circuit, and a second connection node coupled to the first node of the second bias component; and

a fourth MOS transistor, having a control node for receiving the first input signal, a first connection node coupled to the second output port of the driving circuit, and a second connection node coupled to the first node of the second bias component;

wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are of a same conductive type;

wherein the first output port is connected to a first cable having a first impedance matched with an impedance of the first bias component, and matched with an impedance of the second bias component;

wherein the second output port is connected to a second cable having a second impedance matched with the impedance of the first bias component, and matched with the impedance of the second bias component; and

a calibration unit, coupled to the driving units, for activating at least one of the driving units according to an output signal of one of the first output port and the second port of the driving circuit.

2. The driving circuit of claim 1, wherein each of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor is an N-channel MOS (NMOS) transistor.

3. The driving circuit of claim 1, wherein the first input signal and the second input signal are a differential signal pair.

4. The driving circuit of claim 1, wherein at lest one of the first bias component and the second bias component is a resistor, which is matched with the first impedance of the first cable and matched with the second impedance of the second cable.

5. The driving circuit of claim 4, wherein the first bias component and the second bias component are combined to match an impedance of a loading coupled to the first output port or the second output port of the driving circuit.

6. The driving circuit of claim 1, wherein the calibration unit comprises:

a target voltage generator, for generating a target voltage;

a comparator, coupled to the target voltage generator and one of the first output port and the second port of the driving circuit, for comparing a voltage level of the output signal with the target voltage to generating a comparison output; and

a control logic, coupled to the comparator, for generating a control signal to control a number of activated driving units according to the comparison output.

7. The driving circuit of claim 6, wherein the target voltage is set according to at least an impedance of each load driven by the driving circuit and impedances of the first bias component and the second bias component.

8. The driving circuit of claim 6, wherein the control logic comprises:

a clock generator, for generating at least a first clock signal according to a reference clock, wherein when the voltage level of the output signal is substantially equal to the target voltage, the comparison output generated from the comparator stops the clock generator from generating the first clock signal; and

a counter, coupled to the clock generating, for generating a counter value according to the first clock signal, wherein the control signal is derived from the counter value.

9. The driving circuit of claim 6, wherein the control logic comprises:

a control signal generator, coupled to the counter, for converting the counter value into the control signal.

10. The driving circuit of claim 6, wherein the clock generator further generates a second clock signal according to the reference clock, where the first clock signal and the second clock signal are 180 degrees out of phase;

and the comparator comprises;

a sampling and adjusting element, for sampling the target voltage to generate a sampled voltage at an output node according to the first clock signal, and for adjusting the sampled voltage according to a difference between the target voltage and the voltage level of the output signal to thereby generate an adjusted voltage; and

a determining element, coupled to the sampling and adjusting element, for generating the comparison output according to a voltage level at the output node of the sampling and adjusting element.

11. The driving circuit of claim 1, wherein the first reference voltage and the second voltage reference comply with a Mobile Processor Interface (MIPI) standard.

12. A driving circuit, comprising:

a plurality of driving units each coupled between a first reference voltage and a second reference voltage different from the first reference voltage, each driving unit comprising;

a first bias component, having a first node coupled to the first reference voltage, and a second node for outputting a first bias current;

a second bias component, having a first node for draining a second bias current, and a second node coupled to the second reference voltage;

a first metal-oxide-semiconductor (MOS) transistor, having a control node for receiving a first input signal, a first connection node coupled to the second node of the first bias component, and a second connection node coupled to a first output port of the driving circuit;

a second MOS transistor, having a control node for receiving a second input signal, a first connection node coupled to the second node of the first bias component, and a second connection node coupled to a second output port of the driving circuit;

a third MOS transistor, having a control node for receiving the second input signal, a first connection node coupled to the first output port of the driving circuit, and a second connection node coupled to the first node of the second bias component; and

a fourth MOS transistor, having a control node for receiving the first input signal, a first connection node coupled to the second output port of the driving circuit, and a second connection node coupled to the first node of the second bias component;

wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are of a same conductivetype; and

a calibration unit, coupled to the driving units, for activating at least one of the driving units according to an output signal of one of the first output port and the second port of the driving circuit.

13. The driving circuit of claim 12, wherein the calibration unit comprises:

a target voltage generator, for generating a target voltage;

a comparator, coupled to the target voltage generator and one of the first output port and the second port of the driving circuit, for comparing a voltage level of the output signal with the target voltage to generating a comparison output; and

a control logic, coupled to the comparator, for generating a control signal to control a number of activated driving units according to the comparison output.

14. The driving circuit of claim 13, wherein the target voltage is set according to at least an impedance of each load driven by the driving circuit and impedances of the first bias component and the second bias component.

15. The driving circuit of claim 13, wherein the control logic comprises:

a clock generator, for generating at least a first clock signal according to a reference clock, wherein when the voltage level of the output signal is substantially equal to the target voltage, the comparison output generated from the comparator stops the clock generator from generating the first clock signal; and

a counter, coupled to the clock generating, for generating a counter value according to the first clock signal, wherein the control signal is derived from the counter value.

16. The driving circuit of claim 13, wherein the control logic comprises:

a control signal generator, coupled to the counter, for converting the counter value into the control signal.

17. The driving circuit of claim 13, wherein the clock generator further generates a second clock signal according to the reference clock, where the first clock signal and the second clock signal are 180 degrees out of phase;

and the comparator comprises;

a sampling and adjusting element, for sampling the target voltage to generate a sampled voltage at an output node according to the first clock signal, and for adjusting the sampled voltage according to a difference between the target voltage and the voltage level of the output signal to thereby generate an adjusted voltage; and

a determining element, coupled to the sampling and adjusting element, for generating the comparison output according to a voltage level at the output node of the sampling and adjusting element.