Electrical physical layer activity detector

• US 7,990,182 B2
• Filed: 03/18/2008
• Issued: 08/02/2011
• Est. Priority Date: 03/18/2008
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: McLeod, Scott C.
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US12/050,223
• Publication Number:
  US 20090237117A1
• Time in Patent Office: 1,232 Days
• Field of Search: 327/563, 327 65- 67, 327 58- 62, 330/253
• US Class Current: 327/58
• CPC Class Codes: H03F 3/3076 with symmetrical driving of the end stage
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062

Abstract

A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer'"'"'s input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be fully rectified through the output devices of the two buffers, and may be filtered to provide the detected output. The two buffers may be configured in a symmetrical structure that allows for the rejection of common-mode signals when the outputs of the buffers are coupled to a common node.

Claims

1. A detector for detecting differential signal activity, the detector comprising:

a differential input comprising a first input and a second input;

an output configured to provide an output signal of the detector, wherein the output signal is indicative of differential signal activity on the differential input; and

a buffer having an input coupled to the first input of the detector, and comprising output devices configured to provide an output of the buffer, wherein the output of the buffer is coupled to the second input of the detector;

wherein the output devices of the buffer are configured to half-wave rectify a differential input signal present at the differential input, to generate a half-wave rectified first signal; and

wherein the detector is configured to filter the half-wave rectified first signal to generate the output signal of the detector.

2. The detector of claim 1, wherein the input of the buffer and the output of the buffer are configured to have an input voltage developed at the output of the buffer track an input voltage developed at the input of the buffer when a common-mode signal is applied at the differential input of the detector.

3. The detector of claim 1, wherein the differential input is coupled to a twisted-pair wire bus to detect differential signal activity on the twisted-pair wire bus.

4. The detector of claim 1, wherein the buffer comprises a first NMOS device and a second NMOS device, and a first PMOS device and a second PMOS device, wherein the output devices of the buffer comprise the first NMOS device and the first PMOS device.

5. The detector of claim 4, wherein the first NMOS device, the second NMOS device, the first PMOS device, and the second PMOS device are configured to form a translinear loop.

6. The detector of claim 4, wherein a sum of a gate-source voltage developed in the first PMOS device and a gate-source voltage developed in the second NMOS device is equivalent to a sum of a gate-source voltage developed in the first NMOS device and a gate-source voltage developed in the second PMOS device.

7. The detector of claim 4, wherein the first NMOS device and the second PMOS device are configured to conduct a current having a first value equivalent to a value of a second current applied to the source terminal of the first PMOS device, and further equivalent to a value of a third current applied to the source terminal of the second NMOS device.

8. The detector of claim 1, wherein a voltage developed at the input of the buffer is one half of a voltage difference between a supply voltage and a reference voltage.

9. A method for detecting differential signal activity, the method comprising:

receiving a differential input signal;

driving an input and an output of a buffer with the differential input signal;

in response to said driving the input and the output of the buffer with the differential input signal, the output buffer half-wave rectifying the differential input signal, to generate a half-wave rectified signal; and

filtering the half-wave rectified signal to provide an output proportional to a magnitude of the differential input signal to indicate differential signal activity.

10. The method claim 9, further comprising:

receiving a common-mode input signal;

driving the input and the output of the buffer with the common-mode input signal;

developing a first voltage at the output of the buffer and a second voltage at the input of the buffer, the second voltage tracking the first voltage;

wherein in response to said tracking, a current developed in an output stage of the buffer is not rectified, thereby rejecting the common-mode input signal.

11. The method of claim 9,

wherein said driving the input of the buffer comprises applying a remaining portion of the differential input signal to respective gate terminals of a first PMOS device and a first NMOS device configured as an input stage of the buffer;

wherein said driving the output of the buffer comprises applying the portion of the differential input signal that is driving the output of the buffer to respective source terminals of a second NMOS device and a second PMOS device comprised in the output stage of the buffer; and

wherein the first NMOS device, the second NMOS device, the first PMOS device and the second PMOS device are configured to form a translinear loop;

wherein said filtering the half-wave rectified signal comprises providing the output at a drain terminal of the second PMOS device.

12. A low-current circuit for detecting activity on a differential signal line, the low-current circuit comprising:

first and second NMOS devices and first and second PMOS devices forming a translinear loop, wherein respective gate terminals of the first PMOS device and the second NMOS device are coupled to a first node to form an input of the translinear loop, and respective source terminals of the first NMOS device and the second PMOS device are coupled to a second node to form an output of the translinear loop;

differential inputs configured to couple to the differential signal line, and comprising a first input coupled to the first node and a second input coupled to the second node;

control circuitry configured to drive a sum of the gate-source voltage (V_Gs) developed in the first PMOS device and the V_Gs developed in the second NMOS device to equal a sum of the V_Gs developed in the first NMOS device and the V_Gs developed in the second PMOS device; and

an output configured at one of;

a drain terminal of the second PMOS device;

or

a drain terminal of the first NMOS device;

wherein a DC voltage developed at the output is proportional to a size of a voltage difference between the first input of the low-current circuit and the second input of the low-current circuit.

13. The low-current circuit of claim 12, further comprising a first capacitor coupled between the first input of the low-current circuit and the first node, and a second capacitor coupled between the second input of the low-current circuit and the second node.

14. The low-current circuit of claim 12, wherein the control circuitry comprises a voltage divider circuit coupled between a supply voltage and a reference voltage, wherein the first node is coupled to an output node of the voltage divider circuit to develop a voltage at the first node having a value commensurate with one-half of the supply voltage.

15. The low-current circuit of claim 12 further comprising a first load circuit coupled between a supply voltage and a drain terminal of the first NMOS device, and a second load circuit coupled between the drain terminal of the second PMOS device and a reference voltage.

16. The low-current circuit of claim 12, further comprising:

a third node coupled to a source terminal of the first PMOS device and a gate terminal of the first NMOS device;

a fourth node coupled to a source terminal of the second NMOS device and a gate terminal of the second PMOS device;

a first current source configured to apply a first current to the third node; and

a second current source configured to apply a second current to the fourth node;

wherein a current developed in the first NMOS device and a current developed in the second PMOS device have a value equivalent to a value of the first current.

17. A detector circuit having differential inputs and an output, the detector circuit comprising:

a first, second, third, and fourth transistor, each transistor having a respective control terminal and respective first and second channel terminals, wherein the respective control terminals of the first and second transistor are coupled to a first node, the respective first channel terminals of the third and fourth transistors are coupled to a second node, the first channel terminal of the first transistor is coupled to the control terminal of the third transistor, and the first channel terminal of the second transistor is coupled to the control terminal of the fourth transistor; and

control circuitry configured to drive a sum of a channel voltage developed between the control terminal and the first channel terminal of the first transistor and a channel voltage developed between the control terminal and the first channel terminal of the second transistor to equal a sum of a channel voltage developed between the control terminal and the first channel terminal of the third transistor and a channel voltage developed between the control terminal and the first channel terminal of the fourth transistor;

wherein a first input of the differential inputs is coupled to the first node, and a second input of the differential inputs is coupled to the second node;

wherein the output of the detector circuit is provided at one of;

a second channel terminal of the fourth transistor;

or

a second channel terminal of the third transistor;

wherein a DC voltage developed at the output of the detector circuit in response to a differential input signal applied at the differential inputs is proportional to a size of a voltage difference between the first input and the second input.

18. The detector of claim 17, further comprising:

a first load circuit coupled between a supply voltage and a second channel terminal of the third transistor; and

a second load circuit coupled between the second channel terminal of the fourth transistor and a reference voltage.

19. The detector of claim 17, wherein the control circuitry comprises:

a first resistor coupled between a supply voltage and the first node, and a second resistor coupled between a reference voltage and the first node to establish a midpoint voltage between the supply voltage and the reference voltage at the first node.