Switched capacitor notch filter

• US 7,990,209 B2
• Filed: 06/19/2009
• Issued: 08/02/2011
• Est. Priority Date: 06/19/2009
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Romero, Hernan D.
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US12/487,965
• Publication Number:
  US 20100321105A1
• Time in Patent Office: 774 Days
• Field of Search: 327551-559, 327336-337, 327/94, 327/344
• US Class Current: 327/556
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

A switched capacitor notch filter for sampling an input signal using multiple sampling capacitors and multiple non-overlapping time periods. The charge from the sampling capacitors is averaged and transferred to the filter output during another non-overlapping time period.

Claims

1. A switched capacitor notch filter to remove unwanted components within a predetermined frequency range of an input signal, comprising:

a first sampling capacitor having a first terminal selectively coupled to the input signal by a first switch and having a second terminal selectively coupled to a common node by a second switch;

a second sampling capacitor having a first terminal selectively coupled to the input signal by a third switch and having a second terminal selectively coupled to the common node by a fourth switch;

a first reference switch coupled between the second terminal of said first sampling capacitor and a first reference node;

a second reference switch coupled between the first terminal of the first sampling capacitor and a second reference node;

a third reference switch coupled between the second terminal of said second sampling capacitor and said first reference node;

a fourth reference switch coupled between the first terminal of the second sampling capacitor and said second reference node;

an operational amplifier having a first input node coupled to the common node, a second input node, and an output node at which a filtered signal of the filter is provided;

a first feedback capacitor coupled between the output node and the first input node of the operational amplifier; and

a clock signal generator for providing a first clock signal to close the first switch and the first reference switch during a first portion of each clock cycle, a second, non-overlapping clock signal to close the third switch and the third reference switch during a second non-overlapping portion of each clock cycle and an averaging, non-overlapping clock signal to close the second switch, fourth switch, second reference switch, and fourth reference switch during a third non-overlapping portion of each clock cycle, wherein the input signal is not sampled during the third portion of each clock cycle.

2. The filter of claim 1 further comprising a second feedback capacitor that is selectively coupled to said first input node of said operational amplifier by a fifth switch, selectively coupled to said output node of said operational amplifier by a sixth switch, and selectively coupled to said first reference node by a fifth reference switch and a sixth reference switch.

3. The filter of claim 2 wherein the fifth reference switch and sixth reference switch are closed during a selected one of said first portion of said clock cycle or said second portion of said clock cycle.

4. The filter of claim 1 wherein a first reference voltage is provided at the first reference node and a second, different reference voltage is provided at the second reference node.

5. The filter of claim 4 wherein the second reference node is connected to said output node of the operational amplifier.

6. The filter of claim 1 wherein the same reference voltage is connected to the first reference node and the second reference node.

7. The filter of claim 1 wherein said input signal is from a magnetic field sensor.

8. The filter of claim 7 wherein said magnetic field sensor comprises a Hall Effect transducer.

9. The filter of claim 2 wherein the fifth switch and the sixth switch are closed during the averaging portion of each clock cycle.

10. The filter of claim 1 wherein the second reference node is connected to said output node of the operational amplifier.

11. A switched capacitor notch filter to remove unwanted components within a predetermined frequency range of a differential input signal, comprising:

a first sampling capacitor having a first terminal selectively coupled to a first differential input signal by a first switch and having a second terminal selectively coupled to a common node by a second switch;

a second sampling capacitor having a first terminal selectively coupled to the first differential input signal by a third switch and having a second terminal selectively coupled to the common node by a fourth switch;

a first reference switch coupled between the second terminal of said first sampling capacitor and a first reference node;

a second reference switch coupled between the first terminal of the first sampling capacitor and a second reference node;

a third reference switch coupled between the second terminal of said second sampling capacitor and said first reference node;

a fourth reference switch coupled between the first terminal of the second sampling capacitor and said second reference node;

a first differential sampling capacitor having a first terminal selectively coupled to a second differential input signal by a first differential switch and having a second terminal selectively coupled to a differential common node by a second differential switch;

a second differential sampling capacitor having a first terminal selectively coupled to the second differential input signal by a third differential switch and having a second terminal selectively coupled to the differential common node by a fourth differential switch;

a first differential reference switch coupled between the second terminal of said first differential sampling capacitor and a first differential reference node;

a second differential reference switch coupled between the first terminal of the first differential sampling capacitor and a second differential reference node;

a third differential reference switch coupled between the second terminal of said second differential sampling capacitor and said first differential reference node;

a fourth differential reference switch coupled between the first terminal of the second differential sampling capacitor and said second differential reference node;

an operational amplifier having a first input node coupled to the common node, a second input node coupled to said differential common node, a first output node and a second output node across which a filtered signal of the filter is provided;

a first feedback capacitor coupled between the first output node and the first input node of the operational amplifier; and

a first differential feedback capacitor coupled between said second input node and the second output node of said operational amplifier; and

a clock signal generator for providing a first clock signal to close the first, first reference, first differential, and first differential reference switches during a first portion of each clock cycle and a second, non-overlapping clock signal to close the third, third reference, third differential and third differential reference switches during a second non-overlapping portion of each clock cycle, and an averaging, non-overlapping clock signal to close the second, second reference, second differential, second differential reference, fourth, fourth reference, fourth differential, and fourth differential reference switches during an averaging non-overlapping portion of each clock cycle wherein the differential input signal is not sampled during the averaging portion of each clock cycle.

12. The filter of claim 11 wherein a first reference voltage is provided at the first reference node, a second different reference voltage is provided at the second reference node, a third different reference voltage is provided at the first differential reference node, and a fourth different reference voltage is provided at the second differential reference node.

13. The filter of claim 11 wherein the second reference node is connected to the first output node of the operational amplifier and the fourth reference node is connected to the second output node of the operational amplifier.

14. The filter of claim 11 wherein said first and second input signals are from a magnetic field sensor input.

15. The filter of claim 14 wherein said magnetic field sensor comprises a Hall Effect transducer.

16. The filter of claim 11 wherein the same reference voltage is connected to the first reference node, second reference node, first differential reference node, and second differential reference node.

17. The filter of claim 11 further comprising:

a second feedback capacitor that is selectively coupled to said first input node of said operational amplifier by a fifth switch, selectively coupled to said first output node of said operational amplifier by a sixth switch , and selectively coupled to said first reference node by a fifth reference switch and a sixth reference switch; and

a second differential feedback capacitor selectively coupled to the second input node of said operational amplifier by a fifth differential switch and selectively coupled to said second output node of the operational amplifier by a sixth differential switch, and selectively coupled to said first differential reference node by a fifth differential reference switch and a sixth differential reference switch.

18. The filter of claim 17 wherein the fifth switch, fifth differential switch, the sixth switch and the sixth differential switch are closed during the averaging portion of each clock cycle.

19. The filter of claim 17 wherein the fifth reference switch, fifth differential reference switch, the sixth reference switch and the sixth differential reference switch are closed during a selected one of said first portion of said clock cycle or said second portion of said clock cycle.

20. A method of filtering an input signal to remove unwanted components within a predetermined frequency range of the input signal comprising:

sampling the input signal from an input signal terminal to charge a first capacitor during a first time period of a first clock signal and to charge a second capacitor during a second time period of a second clock signal, wherein the first time period and the second time period are non-overlapping sampling time periods; and

coupling said first and second capacitors to an input node of an amplifying circuit comprising an operational amplifier having a feedback capacitor and an output node at which a filtered output signal is provided with switches during a third time period of a third clock signal, wherein the third time period is an averaging time period that does not overlap with any of the plurality of sampling time periods.

21. The method of filtering the input signal of claim 20 further comprising:

coupling a second feedback capacitor in parallel with said feedback capacitor with switches during said averaging time period.

22. A method of filtering a differential input signal to remove unwanted components within a predetermined frequency range of the differential input signal comprising:

sampling a first differential input signal from an input signal terminal to charge a first capacitor during a first time period of a first clock signal and to charge a second capacitor during a second time period of a second clock signal, wherein the first time period and the second time period are non-overlapping sampling time periods;

sampling a second differential input signal from a second input signal terminal to charge a first differential capacitor during the first time period of the first clock signal and to charge a second differential capacitor during the second time period of the second clock signal;

coupling said first and second capacitors to a first input node of an amplifying circuit with switches during an averaging non-overlapping time period, wherein the amplifying circuit comprises an operational amplifier having the first input node, a second input node, a first output node and a second output node across which a differential filtered output signal is provided, a feedback capacitor coupled between the first output node and the first input node and a differential feedback capacitor coupled between the second output node and the second input node; and

coupling first and second differential capacitors to the second input node of the operational amplifier with switches during the averaging non-overlapping time period, wherein the averaging time period does not overlap with any of the plurality of sampling time periods.

23. The method of filtering the differential input signal of claim 22 further comprising:

coupling a second feedback capacitor between said first output node and said first input node of the amplifying circuit with switches during said averaging non-overlapping time period; and

coupling a second differential feedback capacitor between said second output node and said second input node of the amplifying circuit with differential switches during said averaging non-overlapping time period.

24. A switched capacitor notch filter, comprising:

a first sampling capacitor having a first terminal selectively coupled to an input signal by a first switch and having a second terminal selectively coupled to a common node by a second switch;

a second sampling capacitor having a first terminal selectively coupled to the input signal by a third switch and having a second terminal selectively coupled to the common node by a fourth switch;

a third sampling capacitor having a first terminal selectively coupled to the input signal by a seventh switch and having a second terminal selectively coupled to the common node by an eighth switch;

a fourth sampling capacitor having a first terminal selectively coupled to the input signal by a ninth switch and having a second terminal selectively coupled to the common node by a tenth switch;

a first reference switch coupled between the second terminal of said first sampling capacitor and a first reference node;

a second reference switch coupled between the first terminal of the first sampling capacitor and a second reference node;

a third reference switch coupled between the second terminal of said second sampling capacitor and said first reference node;

a fourth reference switch coupled between the first terminal of the second sampling capacitor and said second reference node;

a seventh reference switch coupled between the second terminal of the third sampling capacitor and said first reference node;

an eighth reference switch coupled between the first terminal of the third sampling capacitor and said second reference node;

a ninth reference switch coupled between the second terminal of said fourth sampling capacitor and said first reference node;

a tenth reference switch coupled between the first terminal of the fourth sampling capacitor and said second reference node;

an operational amplifier having a first input node coupled to the common node, a second input node, and an output node at which an output signal of the filter is provided;

a first feedback capacitor coupled between the output node and the first input node of the operational amplifier; and

a clock signal generator for providing a first clock signal to close the first switch and the first reference switch during a first portion of each clock cycle, a second, non-overlapping clock signal to close the third switch and the third reference switch during a second non-overlapping portion of each clock cycle, a third, non-overlapping clock signal to close the seventh switch and the seventh reference switch during a third non-overlapping portion of each clock cycle, a fourth, non-overlapping clock signal to close the ninth switch and the ninth reference switch during a fourth non-overlapping portion of each clock signal, and an averaging, non-overlapping clock signal to close the second switch, fourth switch, eighth switch, tenth switch, _second reference switch, fourth reference switch, eighth reference switch, and tenth reference switch during a fifth non-overlapping portion of each clock cycle.

25. The filter of claim 24 further comprising a second feedback capacitor that is selectively coupled to said first input node of said operational amplifier by a fifth switch, selectively coupled to said output node of said operational amplifier by a sixth switch, and selectively coupled to said first reference node by a fifth reference switch and a sixth reference switch.

26. A switched capacitor notch filter, comprising:

a first sampling capacitor having a first terminal selectively coupled to an input signal by a first switch and having a second terminal selectively coupled to a common node by a second switch;

a second sampling capacitor having a first terminal selectively coupled to the input signal by a third switch and having a second terminal selectively coupled to the common node by a fourth switch;

a third sampling capacitor having a first terminal selectively coupled to the input signal by a seventh switch and having a second terminal selectively coupled to the common node by an eighth switch;

a fourth sampling capacitor having a first terminal selectively coupled to the input signal by a ninth switch and having a second terminal selectively coupled to the common node by a tenth switch;

a first reference switch coupled between the second terminal of said first sampling capacitor and a first reference node;

a second reference switch coupled between the first terminal of the first sampling capacitor and a second reference node;

a third reference switch coupled between the second terminal of said second sampling capacitor and said first reference node;

a fourth reference switch coupled between the first terminal of the second sampling capacitor and said second reference node;

a seventh reference switch coupled between the second terminal of the third sampling capacitor and said first reference node;

an eighth reference switch coupled between the first terminal of the third sampling capacitor and said second reference node;

a ninth reference switch coupled between the second terminal of said fourth sampling capacitor and said first reference node;

a tenth reference switch coupled between the first terminal of the fourth sampling capacitor and said second reference node;

a first differential sampling capacitor having a first terminal selectively coupled to a second input signal by a first differential switch and having a second terminal selectively coupled to a differential common node by a second differential switch;

a second differential sampling capacitor having a first terminal selectively coupled to the second input signal by a third differential switch and having a second terminal selectively coupled to the differential common node by a fourth differential switch;

a third differential sampling capacitor having a first terminal selectively coupled to the second input signal by a seventh differential switch and having a second terminal selectively coupled to the differential common node by an eighth differential switch;

a fourth differential sampling capacitor having a first terminal selectively coupled to the second input signal by a ninth differential switch and having a second terminal selectively coupled to the differential common node by a tenth differential switch;

a first differential reference switch coupled between the second terminal of said first differential sampling capacitor and a first differential reference node;

a second differential reference switch coupled between the first terminal of the first differential sampling capacitor and a second differential reference node;

a third differential reference switch coupled between the second terminal of said second differential sampling capacitor and said first differential reference node;

a fourth differential reference switch coupled between the first terminal of the second differential sampling capacitor and said second differential reference node;

a seventh differential reference switch coupled between the second terminal of the third differential sampling capacitor and said first differential reference node;

an eighth differential reference switch coupled between the first terminal of the third differential sampling capacitor and said second differential reference node;

a ninth differential reference switch coupled between the second terminal of said fourth differential sampling capacitor and said first differential reference node;

a tenth differential reference switch coupled between the first terminal of the fourth differential sampling capacitor and said second differential reference node;

an operational amplifier having a first input node coupled to the common node, a second input node coupled to the differential common node, a first output node and a second output node across which an output signal of the filter is provided;

a first feedback capacitor coupled between the first output node and the first input node of the operational amplifier;

a first differential feedback capacitor coupled between said second input node and the second output node of said operational amplifier; and

a clock signal generator for providing a first clock signal to close the first switch, the first differential switch, the first reference switch, and the first differential reference switch during a first portion of each clock cycle, a second, non-overlapping clock signal to close the third switch, third differential switch, the third reference switch, and the third differential reference switch during a second non-overlapping portion of each clock cycle, a third, non-overlapping clock signal to close the seventh switch, seventh differential switch, the seventh reference switch, and the seventh differential reference switch during a third non-overlapping portion of each clock cycle, a fourth, non-overlapping clock signal to close the ninth switch, the ninth differential switch, the ninth reference switch, and the ninth differential reference switch during a fourth non- overlapping portion of each clock cycle, and an averaging, non-overlapping clock signal to close the second switch, fourth switch, eighth switch, tenth switch, second differential switch, fourth differential switch, eighth differential switch, tenth differential switch, second reference switch, fourth reference switch, eighth reference switch, tenth reference switch, second differential reference switch, fourth differential reference switch, eighth differential reference switch, and tenth differential reference switch during a fifth non-overlapping portion of each clock cycle.

27. A switched capacitor notch filter, comprising:

a first sampling capacitor having a first terminal selectively coupled to an input signal by a first switch and having a second terminal selectively coupled to a common node by a second switch;

a second sampling capacitor having a first terminal selectively coupled to the input signal by a third switch and having a second terminal selectively coupled to the common node by a fourth switch;

a third sampling capacitor having a first terminal selectively coupled to the input signal by a seventh switch and having a second terminal selectively coupled to the common node by an eighth switch;

a fourth sampling capacitor having a first terminal selectively coupled to the input signal by a ninth switch and having a second terminal selectively coupled to the common node by a tenth switch;

a first reference switch coupled between the second terminal of said first sampling capacitor and a first reference node;

a second reference switch coupled between the first terminal of the first sampling capacitor and a second reference node;

a third reference switch coupled between the second terminal of said second sampling capacitor and said first reference node;

a fourth reference switch coupled between the first terminal of the second sampling capacitor and said second reference node;

a seventh reference switch coupled between the second terminal of the third sampling capacitor and said first reference node;

an eighth reference switch coupled between the first terminal of the third sampling capacitor and said second reference node;

a ninth reference switch coupled between the second terminal of said fourth sampling capacitor and said first reference node;

a tenth reference switch coupled between the first terminal of the fourth sampling capacitor and said second reference node;

an operational amplifier having a first input node coupled to the common node, a second input node, and an output node at which an output signal of the filter is provided;

a first feedback capacitor coupled between the output node and the first input node of the operational amplifier; and

a clock signal generator for providing a first clock signal to close the first switch, the first reference switch, the seventh switch, and the seventh reference switch during a first portion of each clock cycle, a second, non-overlapping clock signal to close the third switch, the third reference switch, ninth switch, and the ninth reference switch during a second non-overlapping portion of each clock cycle, a first averaging, non-overlapping clock signal to close the second switch, fourth switch, second reference switch, and fourth reference switch during a third non- overlapping portion of each clock cycle, and a second averaging, non-overlapping clock signal to close the eighth switch, tenth switch, eighth reference switch, and tenth reference switch during a fourth non-overlapping portion of each clock cycle.

28. The filter of claim 27 further comprising a second feedback capacitor that is selectively coupled to said first input node of said operational amplifier by a fifth switch, selectively coupled to said first output node of said operational amplifier by a sixth switch, and selectively coupled to said first reference node by a fifth reference switch and a sixth reference switch.

29. A switched capacitor notch filter, comprising:

a first sampling capacitor having a first terminal selectively coupled to an input signal by a first switch and having a second terminal selectively coupled to a common node by a second switch;

a second sampling capacitor having a first terminal selectively coupled to the input signal by a third switch and having a second terminal selectively coupled to the common node by a fourth switch;

a third sampling capacitor having a first terminal selectively coupled to the input signal by a seventh switch and having a second terminal selectively coupled to the common node by an eighth switch;

a fourth sampling capacitor having a first terminal selectively coupled to the input signal by a ninth switch and having a second terminal selectively coupled to the common node by a tenth switch;

a first reference switch coupled between the second terminal of said first sampling capacitor and a first reference node;

a second reference switch coupled between the first terminal of the first sampling capacitor and a second reference node;

a third reference switch coupled between the second terminal of said second sampling capacitor and said first reference node;

a fourth reference switch coupled between the first terminal of the second sampling capacitor and said second reference node;

a seventh reference switch coupled between the second terminal of the third sampling capacitor and said first reference node;

an eighth reference switch coupled between the first terminal of the third sampling capacitor and said second reference node;

a ninth reference switch coupled between the second terminal of said fourth sampling capacitor and said first reference node;

a tenth reference switch coupled between the first terminal of the fourth sampling capacitor and said second reference node;

a first differential sampling capacitor having a first terminal selectively coupled to a second input signal by a first differential switch and having a second terminal selectively coupled to a differential common node by a second differential switch;

a second differential sampling capacitor having a first terminal selectively coupled to the second input signal by a third differential switch and having a second terminal selectively coupled to the differential common node by a fourth differential switch;

a third differential sampling capacitor having a first terminal selectively coupled to the second input signal by a seventh differential switch and having a second terminal selectively coupled to the differential common node by an eighth differential switch;

a fourth differential sampling capacitor having a first terminal selectively coupled to the second input signal by a ninth differential switch and having a second terminal selectively coupled to the differential common node by a tenth differential switch;

a first differential reference switch coupled between the second terminal of said first differential sampling capacitor and a first differential reference node;

a second differential reference switch coupled between the first terminal of the first differential sampling capacitor and a second differential reference node;

a third differential reference switch coupled between the second terminal of said second differential sampling capacitor and said first differential reference node;

a fourth differential reference switch coupled between the first terminal of the second differential sampling capacitor and said second differential reference node;

a seventh differential reference switch coupled between the second terminal of the third differential sampling capacitor and said first differential reference node;

an eighth differential reference switch coupled between the first terminal of the third differential sampling capacitor and said second differential reference node;

a ninth differential reference switch coupled between the second terminal of said fourth differential sampling capacitor and said first differential reference node;

a tenth differential reference switch coupled between the first terminal of the fourth differential sampling capacitor and said second differential reference node;

an operational amplifier having a first input node coupled to the common node, a second input node coupled to the differential common node, a first output node and a second output node across which an output signal of the filter is provided;

a first feedback capacitor coupled between the first output node and the first input node of the operational amplifier;

a first differential feedback capacitor coupled between said second input node and the second output node of said operational amplifier; and

a clock signal generator for providing a first clock signal to close the first switch, the first reference switch, the first differential switch, the first differential reference switch, the seventh switch, the seventh reference switch, the seventh differential switch, and the seventh differential reference switch during a first portion of each clock cycle, a second, non-overlapping clock signal to close the third switch, the third reference switch, the third differential switch, the third differential reference switch, the ninth switch, the ninth reference switch, the ninth differential switch and the ninth differential reference switch during a second non-overlapping portion of each clock cycle, a first averaging, non-overlapping clock signal to close the second switch, second differential switch, fourth switch, eighth differential switch, second reference switch second differential reference switch, fourth reference switch, and the eighth differential reference switch during a third non-overlapping portion of each clock cycle, and a second averaging, non- overlapping clock signal to close the fourth switch, eighth differential switch, tenth switch, tenth differential switch, eighth reference switch, fourth differential reference switch, tenth reference switch, and tenth differential reference switch during a fourth non-overlapping portion of each clock cycle.

30. The filter of claim 29 further comprising:

a second feedback capacitor that is selectively coupled to said first input node of said operational amplifier by a fifth switch, selectively coupled to said first output node of said operational amplifier by a sixth switch, and selectively coupled to said first reference node by a fifth reference switch and a sixth reference switch; and

a second differential feedback capacitor selectively coupled to the second input node of said operational amplifier by a fifth differential switch and selectively coupled to said second output node of the operational amplifier by a sixth differential switch, and selectively coupled to said third reference node by a fifth differential reference switch and a sixth differential reference switch.