High dynamic range cascaded integration pixel cell and method of operation
First Claim
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1. A semiconductor device comprising:
- a photo-conversion node;
a first charge storage node configured to store charge generated by the photo-conversion node;
a second charge storage node configured to store charge generated by the photo-conversion node when the charge exceeds a limit, wherein the limit is the charge storage capacity of the first charge storage node;
a third charge storage node configured to store charge generated by the photo-conversion node when the charge exceeds the combined storage capacity of the first and second charge storage nodes;
a transistor coupled between the first and second charge storage nodes and configured to transfer charge to the second charge storage node when the charge exceeds the limit; and
a second transistor coupled between the second and third charge storage nodes and configured to transfer charge to the third charge storage node when the charge exceeds the combined storage capacity of the first and second charge storage nodes.
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Abstract
A cascaded imaging storage system for a pixel is disclosed for improving intrascene dynamic range. Charges accumulated in a first capacitor spill over into a second capacitor when a charge storage capacity of the first capacitor is exceeded. A third capacitor may also be provided such that charges accumulated by said second capacitor spill over into the third capacitor when the charge storage capacity of the second capacitor is exceeded.
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Citations
1 Claim
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1. A semiconductor device comprising:
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a photo-conversion node; a first charge storage node configured to store charge generated by the photo-conversion node; a second charge storage node configured to store charge generated by the photo-conversion node when the charge exceeds a limit, wherein the limit is the charge storage capacity of the first charge storage node; a third charge storage node configured to store charge generated by the photo-conversion node when the charge exceeds the combined storage capacity of the first and second charge storage nodes; a transistor coupled between the first and second charge storage nodes and configured to transfer charge to the second charge storage node when the charge exceeds the limit; and a second transistor coupled between the second and third charge storage nodes and configured to transfer charge to the third charge storage node when the charge exceeds the combined storage capacity of the first and second charge storage nodes.
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Specification