Semiconductor device having single-ended sensing amplifier

• US 7,990,793 B2
• Filed: 03/17/2009
• Issued: 08/02/2011
• Est. Priority Date: 03/17/2008
• Status: Expired

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Kajigaya, Kazuhiko
• Primary Examiner(s): Dinh; Son T
• Application Number:
  US12/382,493
• Publication Number:
  US 20090251947A1
• Time in Patent Office: 868 Days
• Field of Search: 365/211, 365/207, 365/189.11
• US Class Current: 365/211
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage.

Claims

1. A semiconductor device comprising:

a sense amplifier including a sensing transistor for amplifying data signal and a control transistor connected to a signal line, the sensing transistor having a gate electrode connected to the signal line for transmitting the data signal and a drain connected to an output line, and the control transistor controlling a potential of the signal line to a predetermined potential before the data signal is transmitted to the signal line;

an internal power supply circuit connected to a source of the control transistor or a source of the sensing transistor; and

a temperature compensation circuit for compensating for temperature dependence of the sensing transistor by controlling an output voltage of the internal power supply circuit.

2. The semiconductor device as claimed in claim 1, wherein at least the sensing transistor and the temperature compensation circuit comprise field-effect transistors.

3. The semiconductor device as claimed in claim 1, wherein the output voltage of the internal power supply circuit is supplied to the source of the control transistor.

4. The semiconductor device as claimed in claim 1, wherein the output voltage of the internal power supply circuit is supplied to the source of the sensing transistor.

5. The semiconductor device as claimed in claim 1, further comprising a memory cell connected to the signal line;

wherein

a portion of a charge of the data signal is transmitted by the signal line by accessing the memory cell.

6. The semiconductor device as claimed in claim 5, wherein the memory cell includes a capacitor for storing an electric charge, and a selecting transistor for selecting the capacitor.

7. The semiconductor device as claimed in claim 6, wherein the predetermined potential is set to a potential at which the signal line transitions in one direction from the predetermined potential by accessing the memory cell, regardless of information of the memory cell.

8. The semiconductor device as claimed in claim 7, wherein the temperature compensation circuit includes:

a monitor circuit for monitoring a threshold voltage value of the sensing transistor;

a conversion circuit for converting the threshold voltage value of the sensing transistor monitored by the monitor circuit into a converted voltage value, according to a transfer ratio determined by a capacitance of the capacitor and a parasitic capacitance of the signal line;

a level shift circuit for level shifting the converted voltage value to a voltage set in advance as the output voltage of the internal power supply circuit at a predetermined temperature; and

a driver circuit for supplying a level-shifted voltage value outputted from the level shift circuit as the output voltage of the internal power supply circuit by adding a current supplying capability to the level-shifted voltage value.

9. The semiconductor device as claimed in claim 8, wherein the temperature compensation circuit further includes an output switch circuit provided in a stage subsequent to the driver circuit for switching its output voltage from the level-shifted voltage to a ground potential after a read signal voltage of the signal line has been generated and after a certain delay time has elapsed.

10. The semiconductor device as claimed in claim 8, wherein

the monitor circuit includes a monitor transistor that is substantially the same size as the sensing transistor and a differential amplifier;

and

a drain of the monitor transistor is connected to a power supply, a constant-current source is connected to the source of the monitor transistor, a source potential of the monitor transistor is supplied to the differential amplifier, a gate of the monitor transistor is connected to an output end of the differential amplifier, and a gate voltage of the monitor transistor is adjusted so that a source potential of the monitor transistor is substantially zero volts.

11. The semiconductor device as claimed in claim 5, wherein

the data comprise information of the memory cell, the signal line comprise a local bit line of the memory cell, the sensing transistor comprise the sense amplifier for first amplifying the information of the memory cell, and the output line connected to the drain of the sensing transistor comprise a global bit line;

and

the semiconductor device has a hierarchical bit line structure formed by the local bit line and the global bit line.

12. The semiconductor device as claimed in claim 11, wherein

a memory cell array is formed by a plurality of the memory cells and a plurality of the sense amplifiers that corresponds to the memory cells;

and

the output of the internal power supply circuit controlled by the temperature compensation circuit is connected in common to the plurality of sense amplifiers that are connected to the local bit lines.

13. The semiconductor device as claimed in claim 1, wherein

the temperature compensation circuit is mounted for each semiconductor chip;

and

a plurality of the semiconductor chips is mounted in the semiconductor device.

14. A semiconductor device comprising:

a memory cell including a storage element for storing information and a selecting transistor for selecting the storage element;

a bit line connected to the memory cell;

a sense amplifier including a sensing transistor for reading data on the bit line and a control transistor connected to the bit line, the sensing transistor having a gate connected to the bit line and a drain connected to an output line, and the control transistor controlling a potential of the bit line to a predetermined potential before the information is read out from the memory cell to the bit line;

an internal power supply circuit connected to a source of the control transistor or a source of the sensing transistor; and

a temperature compensation circuit configured from field-effect transistors for compensating for temperature dependence of the sensing transistor by controlling an output voltage of the internal power supply circuit.

15. The semiconductor device as claimed in claim 14, wherein the output voltage of the internal power supply circuit compensated by the temperature compensation circuit is supplied to the source of the control transistor so as to control the predetermined potential.

16. The semiconductor device as claimed in claim 14, wherein the output voltage of the internal power supply circuit compensated by the temperature compensation circuit is supplied to the source of the sensing transistor so as to operate the sensing transistor.

17. The semiconductor device as claimed in claim 14, wherein

the storage element includes a capacitor for storing an electric charge;

and

the temperature compensation circuit includes;

a monitor circuit for monitoring a threshold voltage value of the sensing transistor;

a conversion circuit for converting the threshold voltage value of the sensing transistor monitored by the monitor circuit into a converted voltage value, according to a transfer ratio determined by a capacitance of the capacitor and a parasitic capacitance of the bit line;

a level shift circuit for level shifting the converted voltage value to a voltage set in advance as the output voltage of the internal power supply circuit at a predetermined temperature; and

a driver circuit for supplying a level-shifted voltage value outputted from the level shift circuit as the output voltage of the internal power supply circuit by adding a current supplying capability to the level-shifted voltage value.

18. The semiconductor device as claimed in claim 17, wherein

the monitor circuit includes a monitor transistor that is substantially the same size as the sensing transistor and a differential amplifier;

and

a drain of the monitor transistor is connected to a power supply, a constant-current source is connected to the source of the monitor transistor, a source potential of the monitor transistor is supplied to the differential amplifier, a gate of the monitor transistor is connected to an output end of the differential amplifier, and a gate voltage of the monitor transistor is adjusted so that a source potential of the monitor transistor is substantially zero volts.

19. The semiconductor device as claimed in claim 14, wherein

a memory cell array is formed by a plurality of the memory cells and a plurality of the sense amplifiers that corresponds to the memory cells;

the data is information of the memory cell, the signal line is a local bit line of the memory cell, the sensing transistor is the sense amplifier for first amplifying the information of the memory cell, and the output line connected to the drain of the sensing transistor is a global bit line;

a hierarchical bit line structure is formed by the local bit line and the global bit line; and

the output of the internal power supply circuit controlled by the temperature compensation circuit is connected in common to the plurality of sense amplifiers that are connected to the local bit lines.

20. A semiconductor device comprising:

a memory cell including a capacitor for storing an electric charge, and a selecting transistor for selecting the capacitor;

a bit line connected to the memory cell;

a sense amplifier including a sensing transistor that works as a single-ended sensing amplifier configured from a field-effect transistor for reading data on the bit line and a control transistor connected to the bit line, the sensing transistor having a gate connected to the bit line and a drain connected to an output line, and the control transistor controlling a potential of the bit line to a predetermined potential before the information is read out from the memory cell to the bit line;

an internal power supply circuit connected to a power supply of the sense amplifier; and

a temperature compensation circuit configured from field-effect transistors for compensating for temperature dependence of the sensing transistor by controlling an output voltage of the internal power supply circuit, wherein

the predetermined voltage of the bit line or the source voltage of the sensing transistor is controlled by the output voltage.

21. A semiconductor apparatus comprising:

an amplifier comprising;

a first transistor for sensing and amplifying a first signal, the first transistor including a first electrode of a principal electrically conducting channel, a second electrode of the principal electrically conducting channel, and a control electrode, the control electrode regulating a current flow between the first electrode and the second electrode of the principal electrically conducting channel, the control electrode connected to a signal line for transmitting the first signal and the first electrode connected to an output line; and

a second transistor connected to the signal line, and the second transistor controlling a potential of the signal line to a predetermined potential before the first signal is transmitted to the signal line, the control transistor including a first electrode of a principal electrically conducting channel, a second electrode of the principal electrically conducting channel, and a control electrode, the control electrode regulating a current flow between the first electrode and the second electrode of the principal electrically conducting channel;

a power supply connected to and supplying power to one of the first and second electrode of at least one of the first transistor and the second transistor; and

a compensation unit for compensating temperature dependence of at least the first transistor by controlling an output voltage of the power supply.

22. The semiconductor device as claimed in claim 21, further comprising a memory cell connected to the signal line,

wherein a portion of a charge of the first signal is transmitted by the signal line by accessing the memory cell, and the memory cell includes a first part for storing an electric charge, and a third transistor for selecting the first part of the memory cell.

23. The semiconductor device as claimed in claim 22, wherein the compensation unit comprises:

a first module for monitoring a threshold voltage value of the first transistor;

a second module for converting the threshold voltage value of the first transistor of the amplifier monitored by the first module into a converted voltage value, according to a transfer ratio determined by a capacitance of the first part of the memory cell and a parasitic capacitance of the signal line;

a third module for level shifting the converted voltage value to a voltage set in advance as the output voltage of the power supply at a predetermined temperature; and

a driver for supplying a level-shifted voltage value outputted from the third module as the output voltage of the power supply by adding a current supplying capability to the level-shifted voltage value.

24. The semiconductor device as claimed in claim 23, wherein

the monitor circuit includes a fourth transistor that is substantially the same size as the first transistor of the amplifier and a differential amplifier, the fourth transistor includes a first electrode of a principal electrically conducting channel, a second electrode of the principal electrically conducting channel, and a control electrode, the control electrode regulating a current flow between the first electrode and the second electrode of the principal electrically conducting channel;

and

one of a first and second electrode of the monitor transistor is connected to the power supply, a constant-current source is connected to the other one of the first and second electrode of the fourth transistor, a source potential of the fourth transistor is supplied to the differential amplifier, the control electrode of the monitor transistor is connected to an output end of the differential amplifier, and a control voltage of the fourth transistor is adjusted so that a source potential of the fourth transistor is substantially zero volts.

25. A method of a semiconductor, the method comprising:

sensing and amplifying an input signal by a first device connected to a signal line;

controlling a potential of the signal line to a predetermined potential before the signal is transmitted to the signal line;

supplying power to one of the first and second devices; and

compensating temperature dependence of the first device by controlling an output voltage of the supplied power.

26. The method as claimed in claim 25, further comprising:

transmitting a portion of a charge of the first signal by the signal line by accessing a memory unit.

storing an electric charge in a first part of the memory unit; and

selecting the first part of the memory unit;

monitoring a threshold voltage value of the first device;

converting the threshold voltage value of the first device into a converted voltage value, according to a transfer ratio determined by a capacitance of the first part of the memory unit and a parasitic capacitance of the signal line;

level shifting the converted voltage value to a voltage set in advance as the output voltage of the supplied power at a predetermined temperature; and

supplying a level-shifted voltage value outputted from the level shifting as the output voltage of the supplied power by adding a current supplying capability to the level-shifted voltage value.