Highly integrated media access control

• US 7,991,010 B2
• Filed: 04/20/2010
• Issued: 08/02/2011
• Est. Priority Date: 09/27/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Nazareth, Sean Francis, Moshar, Hooman, Lansing, Shane Patrick, Pantelias, Niki Roberta, Denney, Lisa Voigt, Horton, John Daniel Jr.
• Primary Examiner(s): Pham; Chi H.
• Assistant Examiner(s): MEW, KEVIN D
• Application Number:
  US12/763,372
• Publication Number:
  US 20100202457A1
• Time in Patent Office: 469 Days
• Field of Search: 370/230, 370/235, 370/389, 370/392, 370/470, 370/471, 370/472, 370/474, 370/476, 370465-466
• US Class Current: 370/474
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/52 by attributing bandwidth to queues
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications

Abstract

A supervisory communications device, such as a headend device within a communications network, monitors and controls communications with a plurality of remote communications devices throughout a widely distributed network. The supervisory device allocates bandwidth on the upstream channels by sending MAP messages over its downstream channel. A highly integrated media access controller integrated circuit (MAC IC) operates within the headend to provide lower level processing on signals exchanged with the remote devices. The enhanced functionality of the MAC IC relieves the processing burden on the headend CPU and increases packet throughput. The enhanced functionality includes header suppression and expansion, DES encryption and decryption, fragment reassembly, concatenation, and DMA operations

Claims

1. An apparatus to process an egress signal within a media access controller integrated circuit (MAC IC), comprising:

an egress postprocessor configured to process a frame of data, the egress postprocessor comprising;

a header postprocessor configured to deconcatenate a header from the frame of data,

a payload header suppression/expansion (PHS) processor configured to expand a payload header suppressed packet from the header based upon one or more PHS rules to provide an expanded frame of data, and

a packet direct memory access (DMA) module configured to send the expanded frame of data for storage in a memory.

2. The apparatus of claim 1, further comprising:

an egress memory controller configured to receive the expanded frame of data and to deliver the expanded frame of data to the memory.

3. The apparatus of claim 2, further comprising:

an input/output (I/O) arbitrator configured to receive the expanded frame of data from the memory and to provide the expanded frame of data to a software application.

4. The apparatus of claim 1, wherein the header postprocessor is further configured to receive the frame of data from a first bus, and wherein the packet DMA module is further configured to send the expanded frame of data over a second bus to be stored in the memory, the first bus being different from the second bus.

5. The apparatus of claim 1, wherein the PHS processor is further configured to expand the payload header suppressed packet according to Data Over Cable Service Interface Specification (DOCSIS) Payload Header Suppression.

9. The apparatus of claim 1, wherein the PHS processor is further configured to receive the one or more PHS rules from the memory.

6. An apparatus to process an egress signal within a media access controller integrated circuit (MAC IC), comprising:

a fragment reassembly controller configured to identify a fragmented frame from a payload of the egress signal and to reassemble one or more fragmented frames to provide a frame of data; and

an egress postprocessor configured to process the frame of data, the egress postprocessor comprising;

a header postprocessor configured to deconcatenate a header from the frame of data, and

a payload header suppression/expansion (PHS) processor configured to expand a payload header suppressed packet from the header based upon one or more PHS rules to provide an expanded frame of data.

7. The apparatus of claim 6, further comprising:

an egress pre-processor configured to perform preliminary signal processing on the egress signal to provide the payload.

8. The apparatus of claim 6, further comprising:

an egress memory controller configured to deliver the frame of data to a memory and to provide the frame of data from the memory to the header postprocessor.

10. A method for processing an egress signal within a media access controller integrated circuit (MAC IC), comprising:

(a) deconcatenating, by the MAC IC, a header from a frame of data;

(b) expanding, by the MAC IC, a payload header suppressed packet from the header based upon one or more payload header suppression/expansion (PHS) rules to provide an expanded frame of data; and

(c) sending, by the MAC IC, the expanded frame of data for storage in a memory.

11. The method of claim 10, further comprising:

(d) receiving, by the MAC IC, the expanded frame of data; and

(e) delivering, by the MAC IC, the expanded frame of data to the memory.

12. The method of claim 11, further comprising:

(f) receiving, by the MAC IC, the expanded frame of data from the memory; and

(g) providing, by the MAC IC, the expanded frame of data to a software application.

13. The method of claim 10, wherein step (a) comprises:

(a)(i) receiving, by the MAC IC, the header from a first bus, and

wherein step (c) comprises;

(c)(i) sending, by the MAC IC, the expanded frame of data over a second bus for storage in the memory, the first bus being different from the second bus.

14. The method of claim 10, wherein step (b) comprises:

(b)(i) expanding, by the MAC IC, the payload header suppressed packet according to Data Over Cable Service Interface Specification (DOCSIS) Payload Header Suppression.

18. The method of claim 10, wherein step (b) comprises:

(b)(i) receiving the one or more PHS rules from the memory.

15. A method for processing an egress signal within a media access controller integrated circuit (MAC IC), comprising:

(a) deconcatenating, by the MAC IC, a header from a frame of data;

(b) expanding, by the MAC IC, a payload header suppressed packet from the header based upon one or more payload header suppression/expansion (PHS) rules to provide an expanded frame of data; and

(c) identifying, by the MAC IC, a fragmented frame from a payload of the egress signal and to reassemble one or more fragmented frames to provide the frame of data.

16. The method of claim 15, further comprising:

(d) performing, by the MAC IC, preliminary signal processing on the egress signal to provide the payload.

17. The method of claim 15, further comprising:

(d) delivering, by the MAC IC, the frame of data to a memory; and

(e) providing, by the MAC IC, the frame of data from the memory to the header postprocessor.