Tamper detection line circuitry for use in authenticating an integrated circuit

• US 7,991,699 B2
• Filed: 11/26/2008
• Issued: 08/02/2011
• Est. Priority Date: 07/15/1997
• Status: Expired due to Fees

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Walmsley, Simon Robert
• Primary Examiner(s): Nguyen; Nga B.
• Application Number:
  US12/324,470
• Publication Number:
  US 20090126030A1
• Time in Patent Office: 979 Days
• Field of Search: 340/870, 326/80, 705/64
• US Class Current: 705/64
• CPC Class Codes: B41J 2/16585 for paper-width or non-reciprocating print heads
• CPC Class Codes: B41J 2/17513 Inner structure
• CPC Class Codes: B41J 2/17546 electronically
• CPC Class Codes: B41J 2/17596 Ink pumps, ink valves
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: G06Q 20/105 involving programming of a portable memory device, e.g. IC cards, "electronic purses"
• CPC Class Codes: G06Q 20/20 Point-of-sale [POS] network systems
• CPC Class Codes: G06Q 20/204 comprising interface for record bearing medium or carrier for electronic funds transfer or payment credit
• CPC Class Codes: G06Q 20/367 involving electronic purses or money safes
• CPC Class Codes: G06Q 20/3674 involving authentication
• CPC Class Codes: G06Q 20/382 insuring higher security of transaction
• CPC Class Codes: G06Q 20/3821 Electronic credentials
• CPC Class Codes: G06Q 20/3829 involving key management
• CPC Class Codes: H04N 1/2112 using still video cameras
• CPC Class Codes: H04N 1/2154 the still video camera incorporating a hardcopy reproducing device, e.g. a printer
• CPC Class Codes: H04N 2101/00 Still video cameras
• CPC Class Codes: H04N 23/00 Cameras or camera modules comprising electronic image sensors; Control thereof
• CPC Class Codes: H04N 5/2628 Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation

Abstract

Provided is tamper detection line circuitry for an authentication integrated circuit for use in authenticating an integrated circuit. The tamper detection line circuitry includes a source of pseudo-random bits, and an XOR gate with two inputs and an output in signal communication with flash memory erase and reset circuits. A complete erasure of the memory is triggered by a 0 from the XOR gate. The circuitry also includes first and second paths arranging the source and XOR gate in signal communication with each other, as well as a number of triggers connected to the respective paths, each trigger configured to detect a physical attack on the authentication integrated circuit, said triggers configured to pull a respective path to 0 if a physical attack is detected.

Claims

1. Tamper detection line circuitry for an authentication integrated circuit for use in authenticating an integrated circuit, the tamper detection line circuitry comprising:

a source of pseudo-random bits;

an XOR gate with two inputs, a first input being the pseudo-random bits from the source and a second input being the inverse of the pseudo-random bits from the source, and an output in signal communication with flash memory erase and reset circuits, where a complete erasure of the memory is triggered by a 0 from the XOR gate;

first and second paths arranging the source and XOR gate in signal communication with each other, the first input being arranged on the first path and the second input being arranged on the second path; and

a number of triggers connected to the respective paths, each trigger configured to detect a physical attack on the authentication integrated circuit, said triggers configured to pull a respective path to 0 if a physical attack is detected,

wherein wires of the first and second paths cover the circuitry of the source.

2. Tamper detection line circuitry as claimed in claim 1, wherein each trigger includes an nMOS transistor attached to GND.

3. Tamper detection line circuitry as claimed in claim 1, wherein the second path has an inverter.

4. Tamper detection line circuitry as claimed in claim 1, wherein the source includes a noise generator circuit.

5. Tamper detection line circuitry as claimed in claim 1, wherein the source operates at a higher frequency than an operating frequency of the authentication integrated circuit.

6. Tamper detection line circuitry as claimed in claim 1, wherein the wires of first and second paths are positioned on a layer above the authentication integrated circuit.