Apparatus and method for identifying device types of series-connected devices of mixed type

• US 7,991,925 B2
• Filed: 02/04/2008
• Issued: 08/02/2011
• Est. Priority Date: 02/13/2007
• Status: Expired due to Fees

• Current Assignee: NovaChips Canada Inc. (NovaChips Co., Ltd.)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Sumi, Shuji, Pyeon, Hong Beom
• Primary Examiner(s): Lee; Chun-Kuan
• Assistant Examiner(s): Huson; Zachary K
• Application Number:
  US12/025,177
• Publication Number:
  US 20080195613A1
• Time in Patent Office: 1,275 Days
• Field of Search: 710/3, 710/8, 710/15
• US Class Current: 710/15
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A memory controller is unaware of device types (DTs) of a plurality (N) of series-connected memory devices in an interconnection configuration. Possible DTs include, e.g., random access memories and Flash memories. First, the memory controller sends a specific DT (“don'"'"'t care”) and an initial number of binary code to the first device of the interconnection configuration and the binary code is propagated through the devices. Each device performs a “+1” calculation regardless of the DT. The last device provides the memory controller with Nד+1” from which the memory controller can obtain the number N of devices in the interconnection configuration. Thereafter, the memory controller sends a search number (SN) of binary code and a search DT for DT matching that propagate through the devices. Each device performs DT match determination of “previous match”, “present match” and “don'"'"'t care match”. Based on the match determination, the SN and search DT are or not modified. The modified or non-modified SN and DT are propagated through the devices. Such processes are repeated. From the propagated SN and DT and the previously recognized number of the devices, the memory controller can identify the DT of each device in the interconnection configuration.

Claims

1. A method for identifying a device type (DT) of first to N-th devices connected in-series in an interconnection configuration, N being an integer greater than one, a signal propagating through the devices, each of the devices having a memory for data store, a type of the memory being associated with a device type (DT) that is undefined, the method comprising:

performing a first propagation by providing a first propagated signal including a binary number to the first device of the interconnection configuration, each of the first to N-th devices incrementing the binary number, an incremented binary number replacing the binary number included in the first propagated signal;

recognizing the number of the devices in the interconnection configuration based on the binary number included in the first propagated signal from the interconnection configuration;

performing a second propagation by providing a second propagated signal including a search DT and a binary search number (SN) to the first device of the interconnection configuration, each each of the first to N-th devices determining whether the search DT matches the DT associated with the device;

modifying the SN included in the second propagated signal in response to a DT match determination result; and

recognizing an address of a device associated with the search DT in the interconnection configuration in response to the SN included in the second propagated signal from the N-th device of the interconnection configuration and to the previously recognized number of the devices of the interconnection configuration in response to the first propagated signal.

2. A method for identifying device types (DTs) of a plurality of devices connected in-series in an interconnection configuration, each of the devices having a memory for data store, a type of the memory being associated with a device type (DT) that is undefined, the method comprising:

issuing an interconnection input signal including a search DT and a binary search number (SN) to one of the series-connected devices, the interconnection input signal being propagated through the devices in the interconnection configuration, the SN and search DT being modifiable during propagation;

determining whether the search DT included in a propagated signal matches the DT associated with the device;

modifying the SN included in the propagated signal in response to a DT match determination result;

modifying the received search DT to another DT in response to the DT match determination result. thereby providing an output search DT with or without being modified; and

recognizing an address of a device associated with the search DT in response to the SN included in the propagated signal from another device of the series-connected devices.

3. The method of claim 2, wherein the step of modifying the received search DT comprises:

replacing the received search DT with a specific DT that matches any one of the DTs.

4. The method of claim 2, further comprising:

holding a DT match determination, thereby indicating a previous match between the search DT and the DT associated with the device.

5. The method of claim 4, further comprising:

determining whether the step of modifying the received SN is performed in response to the held DT match determination; and

determining whether the step of modifying the received search DT is performed in response to the held DT match determination.

6. The method of claim 5, further comprising:

determining a device type of a device based on the search DT and the DT associated with that device, thereby providing a present match between the search DT and the associated DT.

7. The method of claim 6, further comprising:

determining whether the step of modifying the received SN is performed in response to the present match; and

determining whether the step of modifying the received search DT is performed in response to the present match.

8. The method of claim 2, wherein the step of recognizing comprises:

determining the SN as zero or a maximum value in response to the SN included in the propagated signal and the bit information on the SN, the maximum value being defined by the bit information.

9. The method of claim 2, wherein:

the step of issuing comprises;

sending the interconnection input signal including any one of serial and parallel bit signals, the one of bit signals including a search command, the search DT and the SN, the one of bit signals being propagated, the step of modifying the SN comprises;

performing a calculation of the received SN with a pre-defined number to provide a modified SN as the output SN in response to the DT match determination result, and the step of recognizing comprises;

receiving the propagated signal comprising the one of bit signals, the one of bit signals including at least the SN.

10. The method of claim 2, wherein the devices of the interconnection configuration are associated with identical or mixed DTs.

11. The method of claim 2, further comprising:

determining the number of the series-connected devices in the interconnection configuration, with a specific DT that matches any one of the device types,

after the number of the devices is determined, the steps of issuing, determining, modifying and recognizing are performed.

12. A system comprising:

a provider for providing an information input signal including a search device type (DT) and a search number (SN) of binary code;

an interconnection configuration of first to N-th devices connected in series, N being an integer greater than one, each of the devices having a memory for data store, a type of the memory being associated with a device type (DT) that is undefined, one of the interconnection configuration receiving the information input signal which is propagated through the devices of the interconnection configuration, the SN and search DT being modifiable during propagation in response to DT match determination by the devices;

a receiver for receiving an information output signal from another device of the interconnection configuration, the received information output signal being derived from the propagated signal and including the SN being derived from the propagated signal; and

a recognizer for recognizing an address of a device in the interconnection configuration in response to the SN and the search DT. each of the devices comprising;

a determiner for determining whether the search DT included in the propagated signal matches the DT associated with that device; and

a modifier for modifying the SN included in the propagated signal in response to a DT match determination result.

13. The system of claim 12, wherein the determiner comprises:

a match holder for holding a previous match;

a match detector for detecting a DT match based on the search DT, the previous match and the DT associated with that device and providing a DT match determination result that is used by the modifier.

14. The system of claim 13, wherein each of the devices further comprises:

a number modifier for modifying a received SN in response to the determination result, thereby providing an output SN with or without being modified; and

a device type modifier for modifying a received search DT to another DT, thereby providing an output search DT with or without being modified.

15. The system of claim 14, wherein the device type modifier comprises:

a device type replacer for replacing the received search DT with a specific DT that matches any one of the DTs, as the output search DT.

16. The system of claim 12, wherein the recognizer comprises:

a number determiner for determining the SN as zero or a maximum value in response to the SN of the received output signal and the bit information on the SN, the maximum value being defined by the bit information.

17. The system of claim 13, wherein:

the provider is configured to send the input signal comprising any one of serial and parallel bit signals, the one of bit signals including a search command, the search DT and the SN;

each of the devices comprises;

an input connection coupled to the output connection of a previous device or to the provider to receive the propagated signal having the one of bit signals as an incoming signal, and

an output connection coupled to the input connection of a next device or to the receiver to transmit an outgoing signal having the one of bit signals as the propagated signal; and

the receiver is configured to receive the output signal comprising the one of bit signals, the one of bit signals including at least the SN.

18. The system of claim 12, further comprising:

a controller for operations of the provider and the receiver.

19. The system of claim 12, further comprising:

a host system configured to communicate with the provider, wherein;

the provider issues an input signal including information on control to the series-connected devices of the interconnection configuration, the information being used for operations of the devices.

20. An apparatus for identifying a device type (DT) of a device in an interconnection configuration of a plurality of devices connected in-series, each of the devices having a memory for data store, a type of the memory being associated with a device type (DT) that is undefined, the apparatus comprising:

a provider for providing an interconnection input signal including a search DT and a binary search number (SN) to one of the devices in the interconnection configuration, the input signal being propagated from the series-connected devices of the interconnection configuration, the SN and search DT included in a propagated signal being modifiable during propagation in response to DT match determination by the devices; and

a receiver for receiving an interconnection output signal from another device of the interconnection configuration, the received output signal including the SN being derived from the propagated signal; and

a recognizer for recognizing an address of a device in the interconnection configuration in response to the SN included in the received output signal and the search DT.

21. The apparatus of claim 20, wherein each of the devices comprises:

a determiner for determining whether the search DT included in the propagated signal matches the DT associated with that device; and

a modifier for modifying the SN included in the propagated signal in response to a DT match determination result.

22. A machine-readable medium storing commands and instructions which, when executed, cause a processor to perform a method for identifying a device type (DT) of a plurality of devices connected in-series in an interconnection configuration, each of the devices having a memory for data store, a type of the memory being associated with a device type (DT) that is undefined, the method comprising:

issuing an interconnection input signal including a search DT and a binary search number (SN) to one of the series-connected devices, the interconnection input signal being propagated through the devices in the interconnection configuration, the SN and search DT being modifiable during propagation;

determining whether the search DT included in a propagated signal matches the DT associated with the device;

modifying the SN included in the propagated signal in response to a DT match determination result;

modifying the received search DT to another DT in response to the DT match determination result, thereby providing an output search DT with or without being modified; and

recognizing an address of a device associated with the search DT in response to the SN included in the propagated signal from another device of the series-connected devices.