Selecting a scan topology

• US 7,992,064 B2
• Filed: 07/29/2009
• Issued: 08/02/2011
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Primary Examiner(s): Ton; David
• Application Number:
  US12/511,968
• Publication Number:
  US 20100031103A1
• Time in Patent Office: 734 Days
• Field of Search: 702/150, 370/352, 714/726, 714/731, 714/727, 714/729
• US Class Current: 714/727
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

A controller that shares an interface with several other controllers connected in a scan topology in a target system may be selected by receiving a selection event and a selection sequence containing selection criteria from a signal line at each of the controllers, wherein the criteria for selection is broadcast to the controllers. A controller is placed online when the received selection criteria matches an activation criteria of the controller.

Claims

1. A method for selecting a controller comprised in a plurality of controllers connected in a scan topology in a target system, the method comprising:

receiving a selection event and a selection sequence containing selection criteria from a signal line at each of the plurality of controllers, wherein the criteria for selection is broadcast to the plurality of controllers; and

placing a controller online when the received selection criteria matches an activation criteria of the controller.

2. The method of claim 1, wherein the plurality of controllers includes a test controller.

3. The method of claim 2, wherein the selection criteria specifies a topology type and the activation criteria specifies a topology type of the test controller.

4. The method of claim 1, wherein the plurality of controllers includes a controller other than a test controller.

5. The method of claim 1, wherein the selection event and the selection criteria are transmitted serially.

6. The method of claim 1, wherein the signal line connects test mode select pins of the plurality of controllers.

7. The method of claim 1, further comprising receiving a qualification sequence of bit values from the signal line at each of the plurality of controllers prior receiving the selection event.

8. The method of claim 1, further comprising receiving a sequence of bit values from the signal line at each of the plurality of controllers to create a selection.

9. The method of claim 1, further comprising placing the controller offline when the received selection criteria does not match the activation criteria.

10. The method of claim 1, wherein the selection criteria specifies a scan type and the activation criteria specifies a technology type of the controller.

11. The method of claim 1, wherein the selection criteria specifies a specific state within the controller.

12. The method of claim 1, wherein the selection sequence may be dynamically varied in length.

13. The method of claim 1, wherein the selection sequence may modify subsequent signal drive characteristics.

14. The method of claim 1, further comprising modifying subsequent signal drive characteristics in response to the selection event and selection sequence.

15. The method of claim 1, wherein a receiving a selection event comprises:

receiving a clock signal that transitions between a first logic state and a second logic state;

receiving a data signal that contains data synchronized with the clock signal;

detecting two or more edge transitions on the data signal while the clock signal is held at the first logic state;

counting a number of the two or more edge transitions on the data signal while the clock signal is held at the first logic state; and

determining a selection event based on the counted number of edge transitions on the data signal when the clock signal transitions to the second logic state.

16. A method for selecting a controller comprised in a plurality of controllers connected in a scan topology in a target system, the method comprising:

receiving a control event comprising a sequence on a signal line while a second signal is held at a specified logic level;

receiving selection criteria when the control event is a select event; and

entering an online state when the received selection criteria matches selection criteria required by the controller.

17. The method of 16, further comprising receiving a qualification sequence to allow initiation of the control event.

18. The method of 17, further comprising receiving a bit sequence initiating the control event.

19. A digital system, comprising:

at least one functional component with a controller, the controller comprising;

a clock signal and a control signal that may be configured to receive test or debug information from a system under test;

a serial path having one or more bits, the serial path configurable to connect to a data input signal and to a data output signal in a first mode and to the control signal in a second mode;

controller selection criteria, and

control logic coupled to the controller selection criteria, the control logic configured to detect a selection event and selection criteria received on the control signal.

20. The digital system of claim 19, wherein the control logic is configured to select a legacy 1149.1 protocol when the data input signal and the data output signal are connected as a data input/output path of the controller, and to select another protocol when the data input/output path is connected to the control signal.

21. The digital system of claim 19, wherein the selection event and the selection criteria are received together serially.

22. The digital system of claim 19, wherein the control logic is further configured to receive and detect a sequence of bit values that qualify the initiation of a selection sequence by the selection event.

23. The digital system of claim 19, wherein the control logic is further configured to place the controller in an offline mode when the received selection criteria does not match activation criteria of the controller, and to place the controller in an online mode when the received selection criteria matches the activation criteria.