Automatic scan format selection based on scan topology selection

• US 7,992,065 B2
• Filed: 07/29/2009
• Issued: 08/02/2011
• Est. Priority Date: 07/29/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Primary Examiner(s): Ton; David
• Application Number:
  US12/511,998
• Publication Number:
  US 20100031104A1
• Time in Patent Office: 734 Days
• Field of Search: 714/726, 714/731, 714/727, 714/729, 702/150, 370/352
• US Class Current: 714/727
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
• CPC Class Codes: G01R 31/318538 Topological or mechanical aspects
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/36 Preventing errors by testing or debugging software
• CPC Class Codes: G06F 11/3656 using a specific debug interface
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

A method for specifying a signaling protocol to be used by a controller in a group of controllers connected with shared signaling is provided in which the controller is selected based on selection criteria received by the controller and the signaling protocol is specified based on the received selection criteria.

Claims

1. A method for specifying a signaling protocol to be used by a controller comprised in a plurality of controllers connected with shared signaling, the method comprising:

selecting the controller in the plurality of controllers based on selection criteria received by the controller; and

specifying the signaling protocol based on the received selection criteria.

2. The method of claim 1, further comprising:

receiving a selection event and the selection criteria from a signal line at each of the plurality of controllers, wherein the plurality of controllers are connected in parallel to a signal line; and

placing the controller online only when the received selection criteria matches selection criteria of the controller.

3. The method of claim 2, wherein the selection event and the selection criteria are transmitted together serially on the signal line.

4. The method of claim 2, wherein the signal line connects test mode select pins of the plurality of controllers.

5. The method of claim 2, wherein the signal line connects test mode select pins of the plurality of controllers, wherein some of the controllers are test controllers and some of the controllers are another controller type.

6. The method of claim 2, wherein the signal line connects at least one control pin of the plurality of controllers, none of which are test controllers.

7. The method of claim 2, wherein receiving a selection event comprises receiving a bit pattern that is a qualification sequence permitting the initiation of a selection sequence by the selection event at each of the plurality of controllers.

8. The method of claim 2, wherein receiving a selection event comprises receiving a bit pattern that is a selection event, wherein the selection event initiates a selection sequence at each of the plurality of controllers.

9. The method of claim 1, wherein the received selection criteria specifies a scan topology type and the selection criteria of the controller specifies a scan topology type of the controller.

10. The method of claim 2, wherein receiving a selection event comprises:

receiving a clock signal that transitions between a first logic state and a second logic state;

receiving a data signal that contains data synchronized with the clock signal;

detecting two or more edge transitions on the data signal while the clock signal is held at the first logic state;

counting a number of the edge transitions on the data signal while the clock signal is held at the first logic state; and

determining a control event based on the number of edge transitions on the data signal that have been counted at the time the clock signal transitions to the second logic state.

11. The method of claim 10, wherein the edge transitions occur while the clock signal is held at a logic state for an extended period of time.

12. The method of claim 10, wherein the edge transitions occur while the clock signal continues to operate in a constant periodic manner.

13. A method for selecting a protocol format for a controller comprised in a plurality of controllers connected in a scan topology in a target system, the method comprising:

receiving a qualification bit sequence from a signal line at each of the plurality of controllers, wherein the plurality of controllers are connected in parallel to the signal line;

receiving a control event from the signal line at each of the plurality of controllers;

receiving an online selection criteria from the signal line at each of the plurality of controllers when the control event is a selection event;

entering an offline state by a controller of the plurality of controllers when the selection criteria does not match selection criteria of the controller;

entering an online state by the controller when the online selection criteria matches the selection criteria of the controller; and

selecting the protocol format from a plurality of protocol formats supported by the controller based on the online selection criteria received by the controller, wherein the protocol format specifies a signaling protocol used for transfers of control and/or data information.

14. The method of 13, wherein receiving a control event occurs while a clock signal line is held high, wherein the plurality of test controllers are connected in parallel to the clock signal line, and wherein receiving the online selection criteria occurs while the clock signal is toggled in a synchronous manner.

15. The method of 13, wherein the signal line connects test mode select pins of the plurality of controllers and the clock signal line connects clock pins of the plurality of controllers.

16. The method of 14 wherein the signal line connects test mode select pins of test controllers in the plurality of controllers and a control or data pin of other types of controllers in the plurality of controllers and the clock signal line connects clock pins of the plurality of controllers.

17. The method of 14, wherein the signal line connects control or data pins of the plurality of test controllers and the clock signal line connects clock pins of the plurality of controllers.

18. A method for selecting a protocol format for a controller comprised in a plurality of controllers connected in a scan topology in a target system, the method comprising:

receiving a bit sequence constituting a control event from a signal line at each of the plurality of controllers, wherein the plurality of controllers are connected in parallel to the signal line;

receiving selection criteria from the signal line at each of the plurality of controllers when the control event is a selection event;

entering an offline state by a controller of the plurality of test controllers when the received selection criteria does not match selection criteria of the controller;

entering an online state by the controller when the received selection criteria matches the selection criteria of the controller; and

selecting the protocol format from a plurality of protocol formats supported by the controller based on the received selection criteria, wherein the protocol format specifies a signaling protocol used for transfers of control and/or data information.

19. A digital system, comprising:

at least one functional component with a controller, the controller comprising;

a clock input and a control input configured to receive signals from a control system;

a controller scan path having one or more bits, the controller scan path connected to a data input and a data output, wherein the data input and the data output are configured to be coupled to a scan path of a scan topology;

a topology register configured to store a topology type for the controller, and

control logic connected to the topology register, the control logic configured to detect a selection event and selection criteria received on the data input, and further configured to use a scan format of a plurality of scan formats supported by the controller based on the received selection criteria when the received selection criteria matches the selection criteria of the controller, wherein the scan format specifies a signaling protocol.

20. The digital system of claim 19, wherein the control logic is configured to select a series scan format when the data input and data output are coupled in series with the topology scan path, to select a four-wire format when the data input and data output are connected in parallel with the topology scan path, and to select a two-wire format when the data input and data output are not connected to the topology scan path.

21. The digital system of claim 19, wherein the selection event and the selection criteria are received together serially.

22. The digital system of claim 19, wherein the control logic is further configured to receive and detect a sequence of bit values creating a selection event.

23. The digital system of claim 19, wherein the control logic is further configured to place the controller in an offline mode when the received selection criteria does not match the selection criteria, and to place the controller in an online mode when the received selection criteria matches the selection criteria.

24. The system of claim 19, wherein the control logic is further configured to cause the controller to operate as a series connected device when the data input and data output are coupled in series with the topology scan path, to operate as a four-wire parallel connected device when the data input and data output are connected in parallel with the topology scan path, and to operate as a two-wire parallel connected device when the data input and data output are not connected to the topology scan path.

25. The system of claim 19, wherein the control logic is further configured to cause the controller to operate as a series connected device independent of the connectivity or existence of the data input and data output signals.

26. A digital system, comprising:

at least one functional component with a controller, the controller comprising;

a clock signal and a control signal that may be configured to receive test or debug information from a system under test;

a serial path having one or more bits, the serial path connected to the control signal;

controller selection criteria, and

control logic coupled to the controller selection criteria, the control logic configured to detect a selection event and selection criteria received on the control signal and to configure the controller for operation using a protocol selected based on the received selection criteria when the controller is selected.

27. The digital system of claim 26, wherein the selection event and the selection criteria are received together serially.

28. The digital system of claim 26, wherein the control logic is further configured to receive and detect a sequence of bit values that qualify the initiation of a selection sequence by the selection event.

29. The digital system of claim 26, wherein the control logic is further configured to place the controller in an offline mode when the received selection criteria does not match the controller selection criteria, and to place the controller in an online mode when the received selection criteria matches the controller selection criteria.