Method for implementing error-correction codes in non-volatile memory

• US 7,992,071 B2
• Filed: 06/14/2010
• Issued: 08/02/2011
• Est. Priority Date: 01/18/2006
• Status: Expired due to Fees

• Current Assignee: Sandisk China Limited (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Murin, Mark
• Primary Examiner(s): Baderman; Scott T
• Assistant Examiner(s): Ahmed; Enam
• Application Number:
  US12/814,917
• Publication Number:
  US 20100257428A1
• Time in Patent Office: 414 Days
• Field of Search: 714/763
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A method in a data storage device for storing a plurality of data bits into a non-volatile memory includes transforming a plurality of data bits to be stored in a non-volatile memory device to generate a plurality of transformed data bits. The method further includes generating a parity bit corresponding to the plurality of transformed data bits, transforming the parity bit, and storing the plurality of data bits and the transformed parity bit in the non-volatile memory device. Each of the plurality of data bits and the parity bit form an all-one codeword.

Claims

1. A method for storing a plurality of data bits into a non-volatile memory device, the method comprising:

in a data storage device, performing;

transforming a plurality of data bits to be stored in a non-volatile memory device to generate a plurality of transformed data bits;

generating a parity bit corresponding to the plurality of transformed data bits;

transforming the parity bit; and

storing the plurality of data bits and the transformed parity bit in the non-volatile memory device, wherein each of the plurality of data bits and the transformed parity bit form an all-one codeword.

2. The method of claim 1, wherein the transformed parity bit is a complement of the parity bit.

3. The method of claim 1, further comprising applying an error-correction code to the plurality of transformed data bits.

4. The method of claim 3, wherein the error-correction code includes a linear systematic code.

5. The method of claim 1, wherein transforming the plurality of data bits includes generating complements of the plurality of data bits.

6. The method of claim 1, further comprising storing the plurality of transformed data bits within the non-volatile memory device.

7. The method of claim 1, further comprising detecting a data error using the plurality of transformed data bits and the transformed parity bit.

8. The method of claim 1, further comprising indicating an operational error when power to the flash memory device is interrupted during an erasure procedure.

9. The method of claim 1, further comprising applying an error-correction code at the data storage device.

10. The method of claim 1, further comprising applying an error-correction code at a host device coupled to the data storage device.

11. The method of claim 1, further comprising receiving the plurality of data bits at the data storage device from a host device.

12. The method of claim 1, wherein the codeword is represented by a 0xFF hexadecimal value.

13. A data storage device comprising:

a non-volatile memory; and

a memory controller configured to;

transform a plurality of data bits to generate a plurality of transformed data bits;

generate a parity bit corresponding to the plurality of transformed data bits;

transform the parity bit; and

store the plurality of data bits and the transformed parity bit in the non-volatile memory, wherein each of the plurality of data bits and the transformed parity bit form an all-one codeword.

14. The device of claim 13, wherein the transformed parity bit is a complement of the parity bit.

15. The device of claim 13, wherein the plurality of transformed data bits is a plurality of complements of the plurality of data bits.

16. The device of claim 13, further comprising an error-correction code module coupled to the memory controller, wherein the error-correction code module is configured to generate a second parity bit corresponding to the plurality of data bits.

17. The device of claim 16, wherein the memory controller is further configured to transfer the plurality of transformed data bits to the error-correction code module.

18. The device of claim 16, wherein the error-correction code module is included in the memory controller.

19. The device of claim 16, wherein each codeword generated by the error-correction code module from the plurality of data bits includes at least one zero bit value.

20. The device of claim 16, wherein the codeword is represented by a 0xFF hexadecimal value.