Process of manufacturing a piezoelectric actuator for tunable electronic components on a carrier substrate

• US 7,992,271 B2
• Filed: 11/20/2009
• Issued: 08/09/2011
• Est. Priority Date: 10/21/2002
• Status: Expired due to Fees

• Current Assignee: HRL Laboratories LLC (The Boeing Co.)
• Original Assignee: HRL Laboratories LLC (The Boeing Co.)
• Inventors: Mehta, Sarabjit
• Primary Examiner(s): TUGBANG, ANTHONY D
• Application Number:
  US12/622,931
• Publication Number:
  US 20100064493A1
• Time in Patent Office: 627 Days
• Field of Search: 29/253.5, 427/96.2, 427/97.7, 427/98.4, 427/100, 310/324, 310/328, 310330-332
• US Class Current: 29/25.35
• CPC Class Codes: H01G 5/18 due to change in inclination, e.g. by flexing, by spiral wrapping
• CPC Class Codes: H10N 30/03 Assembling devices that include piezoelectric or electrostrictive parts
• CPC Class Codes: H10N 30/073 by fusion of metals or by adhesives
• CPC Class Codes: H10N 30/2041 Beam type
• CPC Class Codes: Y10T 29/42 Piezoelectric device making

Abstract

A processes for manufacturing actuating assembly for tuning a circuit by forming a carrier substrate containing a membrane, a conductive layer, and piezoelectric actuators are disclosed. The process includes the steps of: providing a substrate having a bottom protective layer on a bottom side and etched trenches on a top side; depositing a top protective layer on the top side of the substrate; depositing a first conductive layer on the top protective layer; patterning the first conductive layer; patterning the bottom protective layer to form an etch mask aligned with the patterned first conductive layer; forming a piezoelectric structure on the top side of the substrate; depositing a membrane layer along the top side of the substrate and above the piezoelectric structure; curing the membrane layer; depositing a second conductive layer on the cured membrane layer; depositing a protective photoresist layer on the second conductive layer; patterning and hard-baking the photoresist layer; removing a portion of the substrate from the bottom side of the substrate, forming an etched opening in the substrate; removing a portion of the top protective layer; removing a portion of the second conductive layer to form a patterned second conductive layer; and removing the patterned photoresist layer. Changes in shape of the resulting piezoelectric arrangement allow a deflection of the membrane and a corresponding controllable upward or downward movement of the conductive element.

Claims

1. A process for forming a carrier substrate containing a membrane, a conductive layer, and piezoelectric actuators, comprising the steps of:

providing a substrate having a bottom protective layer on a bottom side and etched trenches on a top side;

depositing a top protective layer on the top side of the substrate;

depositing a first conductive layer on the top protective layer;

patterning the first conductive layer;

patterning the bottom protective layer to form an etch mask aligned with the patterned first conductive layer;

forming a piezoelectric structure on the top side of the substrate;

depositing a membrane layer along the top side of the substrate and above the piezoelectric structure;

curing the membrane layer;

depositing a second conductive layer on the cured membrane layer;

depositing a protective photoresist layer on the second conductive layer;

patterning and hard-baking the photoresist layer;

removing a portion of the substrate from the bottom side of the substrate, forming an etched opening in the substrate;

removing a portion of the top protective layer;

removing a portion of the second conductive layer to form a patterned second conductive layer; and

removing the patterned photoresist layer.

2. The process of claim 1, further comprising a step of removing the patterned first conductive layer.

3. The process of claim 1, wherein the piezoelectric structure is a two-layered piezoelectric structure.

4. The process of claim 1, wherein the top protective layer is a SiN layer.

5. The process of claim 1, wherein the bottom protective layer is a SiN layer.

6. The process of claim 1 wherein, in the step of curing the membrane layer, the membrane layer is cured at about 300 degrees Celsius.

7. The process of claim 1, wherein the first conductive layer is a titanium (Ti) and platinum (Pt) metal film.

8. The process of claim 1, wherein in the step of patterning the first conductive layer, the first conductive layer is patterned into rectangular pads.

9. The process of claim 8, wherein the rectangular pads and the etched opening in the substrate have a lateral dimension, the lateral dimension of the rectangular pads being smaller than the lateral dimension of the etched opening in the substrate.

10. The process of claim 1, wherein the second conductive layer is a titanium (Ti) and platinum (Pt) film.

11. The process of claim 1, wherein the step of removing the portion of the substrate from the bottom side of the substrate, forming the etched opening in the substrate, is performed by immersing the substrate in a KOH solution at about 100 degrees Celsius.

12. The process of claim 1, wherein the steps of removing the portion of the top protective layer and removing the portion of the second conductive layer are performed by successively immersing the substrate in a buffered oxide etchant and metal etchant solution.

13. The process of claim 1, wherein the steps of removing the portion of the top protective layer and removing the portion of the second conductive layer are performed by successively immersing the substrate in a buffered oxide etchant solution and by dry etching.

14. The process of claim 1, wherein the step of removing the patterned photoresist layer is performed by spraying with acetone and spin drying.

15. The process of claim 1, wherein the membrane layer is a polymide membrane.

16. The process of claim 1, further comprising the step of bonding the carrier substrate containing the membrane, the conductive layer, and the piezoelectric actuators obtained after the step of removing the patterned photoresist layer to a substrate containing a trench and a metal circuit.

17. The process of claim 16, wherein the step of bonding the carrier substrate to a substrate containing the trench and the metal circuit comprises the step of providing a gold layer on at least one substrate between the carrier substrate and the substrate containing the trench and the metal circuit.

18. The process of claim 17, wherein the step of bonding the carrier substrate and the substrate containing the trench and the metal circuit further comprises the steps of pressing the carrier substrate on the substrate containing the trench and the metal circuit and heating the pressed substrates.