CMOS devices having dual high-mobility channels

• US 7,993,998 B2
• Filed: 03/06/2008
• Issued: 08/09/2011
• Est. Priority Date: 03/06/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chen, Ding-Yuan
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US12/043,588
• Publication Number:
  US 20090227078A1
• Time in Patent Office: 1,251 Days
• Field of Search: 438/199, 438/216, 438/218, 438/221, 438/222, 438/226, 438/230, 257/E21.632
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first and a second metal-oxide-semiconductor (MOS) device. The step of forming the first MOS device includes forming a first silicon germanium layer over the first region of the semiconductor substrate; forming a silicon layer over the first silicon germanium layer; forming a first gate dielectric layer over the silicon layer; and patterning the first gate dielectric layer to form a first gate dielectric. The step of forming the second MOS device includes forming a second silicon germanium layer over the second region of the semiconductor substrate; forming a second gate dielectric layer over the second silicon germanium layer with no substantially pure silicon layer therebetween; and patterning the second gate dielectric layer to form a second gate dielectric.

Claims

1. A method for forming a semiconductor structure, the method comprising:

providing a silicon substrate comprising an NMOS region and a PMOS region;

epitaxially growing a first silicon germanium layer over the silicon substrate, wherein the first silicon germanium layer comprises a first portion over the NMOS region, and a second portion over the PMOS region;

epitaxially growing a silicon-containing semiconductor layer over the first silicon germanium layer, wherein a germanium percentage in the silicon-containing semiconductor is lower than a germanium percentage in the first silicon germanium layer;

forming a first gate dielectric layer over the silicon-containing semiconductor layer;

forming a first gate electrode layer over the first gate dielectric layer;

removing the first gate electrode layer, the first gate dielectric layer, and the silicon-containing semiconductor layer from over the PMOS region;

forming a second gate dielectric layer, wherein the second gate dielectric layer comprises at least a portion over the second portion of the first silicon germanium layer;

forming a second gate electrode layer over the second gate dielectric layer;

patterning the first gate dielectric layer and the first gate electrode layer to form a first gate stack; and

patterning the second gate dielectric layer and the second gate electrode layer to form a second gate stack.

2. The method of claim 1, wherein the steps of forming the second gate electrode layer and the second gate dielectric layer comprises:

blanket forming the second gate dielectric layer;

blanket forming the second gate electrode layer; and

removing the second gate electrode layer and the second gate dielectric layer from over the NMOS region.

3. The method of claim 1, wherein the first gate dielectric layer comprises lanthanum and is free from aluminum, and the second gate dielectric layer comprises aluminum and is free from lanthanum.

4. The method of claim 1 further comprising, after the step of removing the first gate electrode layer, the first gate dielectric layer, and the silicon-containing semiconductor layer from over the PMOS region, epitaxially growing a second silicon germanium layer over and contacting the first silicon germanium layer.

5. The method of claim 1, wherein the silicon-containing semiconductor layer is a substantially pure silicon layer.

6. The method of claim 1, wherein the silicon-containing semiconductor layer is a silicon germanium layer.

7. The method of claim 1, wherein before the step of patterning the second gate dielectric layer and the second gate electrode layer, the second gate dielectric layer and the second gate electrode layer extend to directly over remaining portions of the first gate dielectric layer and the first gate electrode layer.

8. The method of claim 1, wherein after the step of removing the silicon-containing semiconductor layer from over the PMOS region, at least a layer of the silicon-containing semiconductor layer is removed from directly over the NMOS region.

9. A method for forming a semiconductor structure, the method comprising:

providing a silicon substrate comprising an NMOS region and a PMOS region;

epitaxially growing a first silicon germanium layer over the silicon substrate, wherein the first silicon germanium layer comprises a first portion over the NMOS region, and a second portion over the PMOS region;

epitaxially growing a substantially pure silicon layer over the first silicon germanium layer;

forming a first gate dielectric layer over the substantially pure silicon layer;

forming a first gate electrode layer over the first gate dielectric layer;

removing the first gate electrode layer, the first gate dielectric layer, and the substantially pure silicon layer from over the PMOS region, wherein the substantially pure silicon layer is not removed from over the NMOS region;

after the step of removing, epitaxially growing a second silicon germanium layer over and contacting the first silicon germanium layer;

forming a second gate dielectric layer, wherein the second gate dielectric layer comprises at least a portion directly over the second portion of the first silicon germanium layer;

forming a second gate electrode layer over the second gate dielectric layer;

patterning the first gate dielectric layer and the first gate electrode layer to form a first gate stack; and

patterning the second gate dielectric layer and the second gate electrode layer to form a second gate stack.

10. The method of claim 9, wherein the steps of forming the second gate electrode layer and the second gate dielectric layer comprises:

blanket forming the second gate dielectric layer; and

blanket forming the second gate electrode layer.

11. The method of claim 9, wherein the first gate dielectric layer comprises lanthanum and is free from aluminum, and the second gate dielectric layer comprises aluminum and is free from lanthanum.