High-K/metal gate CMOS finFET with improved pFET threshold voltage

• US 7,993,999 B2
• Filed: 11/09/2009
• Issued: 08/09/2011
• Est. Priority Date: 11/09/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Faltermeier, Johnathan E., Khakifirooz, Ali, Cheng, Kangguo, Doris, Bruce B., Basker, Veeraraghavan S.
• Primary Examiner(s): Pham; Long
• Application Number:
  US12/614,906
• Publication Number:
  US 20110108920A1
• Time in Patent Office: 638 Days
• Field of Search: 438/199, 438/151, 438/216
• US Class Current: 438/199
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

Claims

1. A method for fabrication of fin devices for an integrated circuit, comprising:

forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures;

epitaxially depositing a donor material on the exposed sidewalls of the fin structures;

applying a condensation process to move the donor material through the sidewalls into the semiconductor material;

removing the donor material; and

forming a field effect transistor from the fin structure.

2. The method as recited in claim 1, wherein the semiconductor material includes silicon and the donor material includes germanium.

3. The method as recited in claim 1, wherein forming fin structures includes employing a spacer image transfer (SIT) process to form the fin structures having a width less than a minimum features size achievable by lithography.

4. The method as recited in claim 1, wherein epitaxially depositing a donor material includes epitaxially depositing silicon germanium.

5. The method as recited in claim 1, wherein applying a condensation process includes applying an oxidation condensation process to push the donor material into the fin structure.

6. The method as recited in claim 1, wherein forming a field effect transistor from the fin structure includes forming a high-dielectric constant gate dielectric and a gate conductor over the fin structure.

7. The method as recited in claim 1, wherein epitaxially depositing a donor material includes depositing the donor material on a (110) surface.

8. The method as recited in claim 1, wherein removing the donor material maintains a width dimension of the fin structure.

9. The method as recited in claim 1, wherein applying a condensation process includes accommodating the donor material in the semiconductor material to cause a strain in the semiconductor material of the fin structures.

10. A method for fabrication of fin devices for an integrated circuit, comprising:

forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures;

masking a first set of fin structures;

epitaxially depositing a donor material on the exposed sidewalls of a second set of fin structures having exposed sidewalls;

applying a condensation process to move the donor material through the sidewalls into the semiconductor material for the second set of fin structures such that accommodation of the donor material causes a strain in the semiconductor material of the second set of fin structures;

removing the donor material;

removing a mask from the first set of fin structures; and

forming n-type field effect transistors from the first set of fin structures and p-type field effect transistors from the second set of fin structures.

11. The method as recited in claim 10, wherein the semiconductor material includes silicon and the donor material includes germanium.

12. The method as recited in claim 10, wherein forming fin structures includes employing a spacer image transfer (SIT) process to form the fin structures having a width less than a minimum features size achievable by lithography.

13. The method as recited in claim 10, wherein epitaxially depositing a donor material includes epitaxially depositing silicon germanium.

14. The method as recited in claim 10, wherein applying a condensation process includes applying an oxidation condensation process to push the donor material into the second set of fin structures.

15. The method as recited in claim 10, wherein forming n-type field effect transistors from the first set of fin structures and p-type field effect transistors from the second set of fin structures includes forming a high-dielectric constant gate dielectric and a gate conductor over the fin structures.

16. The method as recited in claim 10, wherein epitaxially depositing a donor material includes depositing the donor material on a (110) surface.

17. The method as recited in claim 10, wherein removing the donor material maintains a width dimension of the fin structures.

18. The method as recited in claim 10, wherein the p-type field effect transistor meets a suitable threshold voltage to function with the n-type field effect transistor as a complementary metal oxide semiconductor (CMOS) device.

19. A method for fabrication of fin devices for an integrated circuit, comprising:

forming fin structures in a silicon layer of a silicon-on-insulator substrate exposing sidewalls of the fin structures;

masking a first set of fin structures;

epitaxially depositing a Silicon-Germanium (SiGe) on the exposed sidewalls of a second set of fin structures having exposed sidewalls;

applying an oxidation condensation process to move Germanium (Ge) through the exposed sidewalls of the second set of fin structures;

removing deposited SiGe from the exposed sidewalls;

removing a mask from the first set of fin structures; and

forming n-type field effect transistors (nFET) from the first set of fin structures and p-type field effect transistors (p-FET) from the second set of fin structures such that a complementary metal oxide semiconductor (CMOS) device is fabricated wherein the n-FET includes a silicon active area and the p-FET include a SiGe active area.

20. The method as recited in claim 19, wherein forming fin structures includes employing a spacer image transfer (SIT) process to form the fin structures having a width less than a minimum features size achievable by lithography.

21. The method as recited in claim 19, wherein forming n-type field effect transistors from the first set of fin structures and p-type field effect transistors from the second set of fin structures includes forming a high-dielectric constant gate dielectric and a gate conductor over the fin structures.

22. The method as recited in claim 19, wherein epitaxially depositing includes depositing the SiGe on a surface normal to a channel direction of the p-type field effect transistor.

23. The method as recited in claim 19, wherein removing the donor material maintains a width dimension of the fin structures, wherein the p-type field effect transistor meets a suitable threshold voltage to function with the n-type field effect transistor as the CMOS device.