High-mobility trench MOSFETs

• US 7,994,005 B2
• Filed: 11/01/2007
• Issued: 08/09/2011
• Est. Priority Date: 11/01/2007
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hébert, François
• Primary Examiner(s): Vu; David
• Application Number:
  US11/934,040
• Publication Number:
  US 20090114949A1
• Time in Patent Office: 1,377 Days
• Field of Search: 438/212, 438268-270, 257328-331, 257/335, 257/341, 257/E21.418, 257/E29.256
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility.

Claims

1. A method for manufacturing a high-mobility vertical trenched DMOS comprising:

a) forming an N-type epitaxial (N-epi layer on top of an N+ substrate;

b) forming a trench mask on top of the N-epi layer

c) etching the N-epi layer through the trench mask to a predetermined depth to form a trench;

d) filling the trench with a conductive material to form a gate;

e) forming SiGe region proximate to the gate on a sidewall of the trench but not on a bottom of the trench or a surface of the N-epi laver, wherein the SiGe region is configured to increase a mobility of charge carriers in a channel region, wherein forming the SiGe region comprises;

forming an oxide spacer on the trench sidewall;

isotropically etching a portion of the N-epi layer at a bottom of the trench;

selectively growing an N-type SiGe region on the portion of the N-epi layer that was isotropically etched;

etching the oxide spacer and the trench mask; and

forming a gate oxide layer on the N-type SiGe on the sidewall of the trench; and

f) forming a P-body layer on the surface of the N-epi layer.

2. The method of claim 1 wherein step d) is performed before step e).

3. The method of claim 2 further comprising, before step d):

removing the trench mask; and

forming a gate oxide on the gate.

4. The method of claim 3, wherein step f) includes:

implanting and diffusing the top region of the N-epi layer to form the P-body layer; and

forming a poly oxide layer on top of the gate; and

etching the oxide layer on top of the P-body layer.

5. The method of claim 4, further comprising, after step f):

selectively growing N+ SiGe region on top of the P-body layer; and

etching back the N+ SiGe region to a predetermined width to form a source region.

6. The method of claim 2 further comprising forming a gate oxide before step d).

7. The method of claim 6, wherein step f) includes:

implanting and diffusing a top region of the N-epi layer to form the P-body layer;

removing the trench mask; and

forming an oxide layer over the gate.

8. The method of claim 7, further comprising, after step f):

selectively growing N+ SiGe region on top of the P-body layer; and

etching back the N+ SiGe region to a predetermined width to form a source region.

9. The method of claim 1, wherein step e) is performed before step d).