High-mobility trench MOSFETs
First Claim
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1. A method for manufacturing a high-mobility vertical trenched DMOS comprising:
- a) forming an N-type epitaxial (N-epi layer on top of an N+ substrate;
b) forming a trench mask on top of the N-epi layerc) etching the N-epi layer through the trench mask to a predetermined depth to form a trench;
d) filling the trench with a conductive material to form a gate;
e) forming SiGe region proximate to the gate on a sidewall of the trench but not on a bottom of the trench or a surface of the N-epi laver, wherein the SiGe region is configured to increase a mobility of charge carriers in a channel region, wherein forming the SiGe region comprises;
forming an oxide spacer on the trench sidewall;
isotropically etching a portion of the N-epi layer at a bottom of the trench;
selectively growing an N-type SiGe region on the portion of the N-epi layer that was isotropically etched;
etching the oxide spacer and the trench mask; and
forming a gate oxide layer on the N-type SiGe on the sidewall of the trench; and
f) forming a P-body layer on the surface of the N-epi layer.
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Abstract
High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility.
13 Citations
9 Claims
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1. A method for manufacturing a high-mobility vertical trenched DMOS comprising:
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a) forming an N-type epitaxial (N-epi layer on top of an N+ substrate; b) forming a trench mask on top of the N-epi layer c) etching the N-epi layer through the trench mask to a predetermined depth to form a trench; d) filling the trench with a conductive material to form a gate; e) forming SiGe region proximate to the gate on a sidewall of the trench but not on a bottom of the trench or a surface of the N-epi laver, wherein the SiGe region is configured to increase a mobility of charge carriers in a channel region, wherein forming the SiGe region comprises; forming an oxide spacer on the trench sidewall; isotropically etching a portion of the N-epi layer at a bottom of the trench; selectively growing an N-type SiGe region on the portion of the N-epi layer that was isotropically etched; etching the oxide spacer and the trench mask; and forming a gate oxide layer on the N-type SiGe on the sidewall of the trench; and f) forming a P-body layer on the surface of the N-epi layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification