Silicon carbide semiconductor device including deep layer

• US 7,994,513 B2
• Filed: 04/16/2009
• Issued: 08/09/2011
• Est. Priority Date: 04/17/2008
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Okuno, Eiichi, Yamamoto, Kensaku
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US12/385,715
• Publication Number:
  US 20090261350A1
• Time in Patent Office: 845 Days
• Field of Search: 257/77, 257/133, 257328-342, 257/E21.218, 257/252, 257/345, 257/23.033, 257/69, 257/29.04, 257/21, 257/104, 257/174, 257/175, 257/301, 257/409, 257/492, 257/493, 257/E21.054, 257/29.169, 257/346
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench sandwiched by each of the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer located under the base region and extending to a depth deeper than the trench. The deep layer is formed into a lattice pattern.

Claims

1. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, the substrate having one of a first conductivity type and a second conductivity type, the substrate having first and second opposing surfaces;

a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate;

a base region located on the drift layer, the base region made of silicon carbide and having the second conductivity type;

a source region located on the base region, the source region made of silicon carbide, the source region having the first conductive type and having an impurity concentration greater than the impurity concentration of the drift layer;

a trench extending to a depth deeper than the base region and the source region, the trench being sandwiched by each of the base region and source region;

a channel layer located on a sidewall of the trench, the channel layer made of silicon carbide and having the first conductivity type;

a gate insulating layer located on a surface of the channel layer so as to be apart from the base region;

a gate electrode located on the gate insulating layer in the trench;

a source electrode electrically coupled with the source region and the base region;

a drain electrode located on the second surface of the substrate; and

a deep layer located under the base region and extending to a depth deeper than the trench, the deep layer having the second conductivity type, the deep layer formed into a lattice pattern in such a manner that sections of the deep layer are formed along a first direction, the other sections of the deep layer are formed along a second direction, and the first direction and second direction are inclined at an approximately same angle to the sidewall of the trench in opposite directions, wherein

an accumulation channel is provided at the channel layer on the sidewall of the trench and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.

2. The silicon carbide semiconductor device according to claim 1, wherein

the deep layer has an impurity concentration greater than or equal to an impurity concentration of the base region.

3. The silicon carbide semiconductor device according to claim 1, further comprising

a current diffusion layer located between the base region and the drift layer, wherein:

the current diffusion layer is made of silicon carbide and has the first conductivity type; and

the current diffusion layer has an impurity concentration greater than or equal to the impurity concentration of the drift layer.

4. The silicon carbide semiconductor device according to claim 3, wherein

the trench penetrating the current diffusion layer to the drift layer.

5. The silicon carbide semiconductor device according to claim 3, wherein

the deep layer penetrating the current diffusion layer and being in contact with the base region.

6. The silicon carbide semiconductor device according to claim 1, wherein

the impurity concentration of the drift layer decreases in a direction from the substrate toward the base region.

7. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, the substrate having one of a first conductivity type and a second conductivity type, the substrate having first and second opposing surfaces;

a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate;

a base region located on the drift layer, the base region made of silicon carbide and having the second conductivity type;

a source region located on the base region, the source region made of silicon carbide, the source region having the first conductive type and having an impurity concentration greater than the impurity concentration of the drift layer;

a trench extending to a depth deeper than the base region and the source region, the trench being sandwiched by each of the base region and source region;

a channel layer located on a sidewall of the trench, the channel layer made of silicon carbide and having the first conductivity type;

a gate insulating layer located on a surface of the channel layer so as to be apart from the base region;

a gate electrode located on the gate insulating layer in the trench;

a source electrode electrically coupled with the source region and the base region;

a drain electrode located on the second surface of the substrate; and

a deep layer located under the base region and extending to a depth deeper than the trench, the deep layer having the second conductivity type, the deep layer formed into a honeycomb pattern including a plurality of hexagonal shapes, a diagonal line passing through a center of each of the plurality of hexagonal shapes being approximately perpendicular to the sidewall of the trench, wherein

an accumulation channel is provided at the channel layer on the sidewall of the trench and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.

8. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, the substrate having one of a first conductivity type and a second conductivity type, the substrate having first and second opposing surfaces;

a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate;

a base region located on the drift layer, the base region made of silicon carbide and having the second conductivity type;

a source region located on the base region, the source region made of silicon carbide, the source region having the first conductive type and having an impurity concentration greater than the impurity concentration of the drift layer;

a trench extending to a depth deeper than the base region and the source region, the trench being sandwiched by each of the base region and source region;

a gate insulating layer located on a surface of the trench;

a gate electrode located on the gate insulating layer in the trench;

a source electrode electrically coupled with the source region and the base region;

a drain electrode located on the second surface of the substrate; and

a deep layer located under the base region and extending to a depth deeper than the trench, the deep layer having the second conductivity type, the deep layer formed into a lattice pattern in such a manner that sections of the deep layer are formed along a first direction, the other sections of the deep layer are formed along a second direction, and the first direction and second direction are inclined at an approximately same angle to the sidewall of the trench in opposite directions, wherein

an inversion channel is provided at a surface portion of the base region located on a sidewall of the trench and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.

9. A silicon carbide semiconductor device comprising:

a substrate made of silicon carbide, the substrate having one of a first conductivity type and a second conductivity type, the substrate having first and second opposing surfaces;

a drift layer located on the first surface of the substrate, the drift layer made of silicon carbide, the drift layer having the first conductivity type and having an impurity concentration less than an impurity concentration of the substrate;

a base region located on the drift layer, the base region made of silicon carbide and having the second conductivity type;

a source region located on the base region, the source region made of silicon carbide, the source region having the first conductive type and having an impurity concentration greater than the impurity concentration of the drift layer;

a trench extending to a depth deeper than the base region and the source region, the trench being sandwiched by each of the base region and source region;

a gate insulating layer located on a surface of the trench;

a gate electrode located on the gate insulating layer in the trench;

a source electrode electrically coupled with the source region and the base region;

a drain electrode located on the second surface of the substrate; and

a deep layer located under the base region and extending to a depth deeper than the trench, the deep layer having the second conductivity type, the deep layer formed into a honeycomb pattern including a plurality of hexagonal shapes, a diagonal line passing through a center of each of the plurality of hexagonal shapes being approximately perpendicular to the sidewall of the trench, wherein

an inversion channel is provided at a surface portion of the base region located on a sidewall of the trench and electric current flows between the source electrode and the drain electrode through the source region and the drift layer by controlling a voltage applied to the gate electrode.