Integrated capacitor with tartan cross section

• US 7,994,610 B1
• Filed: 11/21/2008
• Issued: 08/09/2011
• Est. Priority Date: 11/21/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Quinn, Patrick J.
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): HUBER, ROBERT T
• Application Number:
  US12/276,291
• Time in Patent Office: 991 Days
• Field of Search: 257/307, 257/308, 257/532, 257/E27.048, 257/E21.008, 257/534, 361/306.1, 361/306.3, 438/396
• US Class Current: 257/532
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/86 having horizontal extensions
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A capacitor in an IC has a first layer of conductive strips extending along a first direction (Z-direction). A first plurality of conductive strips in the first layer forms a portion a first node of the capacitor and alternates with a second plurality of conductive strips forming a portion of a second node of the capacitor. A plate layer adjacent to the first layer has a third plurality of conductive strips forming a portion the first node. Each strip in the third plurality of conductive strips is adjacent to another strip forming a part of the first node. The strips in the plate layer extend along a second direction (X-direction) orthogonal to the first direction. A first via electrically connects a first conductive strip in the first plurality of conductive strips in the first layer to a second conductive strip in the plate layer.

Claims

1. A capacitor in an integrated circuit (“

IC”

) comprising;

a first layer of conductive strips extending along a first direction including a first plurality of conductive strips forming a first portion of a first node of the capacitor alternating with a second plurality of conductive strips forming a first portion of a second node of the capacitor;

a plate layer adjacent to the first layer, the plate layer including a third plurality of conductive strips forming a second portion of the first node, each strip in the third plurality of conductive strips being next to another strip in the third plurality of conductive strips in the plate layer and extending along a second direction orthogonal to the first direction; and

a first via electrically connecting a first conductive strip in the first plurality of conductive strips in the first layer to a second conductive strip in the plate layer.

2. The capacitor of claim 1 further comprising

a second plate layer of conductive strips extending along the second direction, the first layer of conductive strips being disposed between the plate layer and the second plate layer, the second plate layer including a fourth plurality of conductive strips forming a second portion of the second node, wherein each strip in the fourth plurality of conductive strips is next to another strip in the fourth plurality of conductive strips in the second plate layer;

and

a second via electrically connecting a third conductive strip in the second plurality of conductive strips in the first layer to a fourth conductive strip in the second plate layer.

3. The capacitor of claim 2 further comprising

a third via electrically connecting the fourth conductive strip in the second plate layer to a fifth conductive strip in the second plurality of conductive strips in the first layer.

4. The capacitor of claim 1 further comprising

a second via electrically connecting the second conductive strip in the plate layer to a third conductive strip in the first plurality of conductive strips in the first layer.

5. The capacitor of claim 4 further comprising

a third via electrically connecting a fourth conductive strip in the third plurality of conductive strips in the plate layer to the first conductive strip in the first plurality of conductive strips in the first layer.

6. The capacitor of claim 1 further comprising a second layer of conductive strips, the plate layer being disposed between the first layer of conductive strips and the second layer of conductive strips, the second layer of conductive strips including a fourth plurality of conductive strips forming a third portion of the first node alternating with a fifth plurality of conductive strips forming a second portion of the second node, the conductive strips in the second layer extending along the first direction.

7. The capacitor of claim 6 further comprising a second via electrically connecting the second conductive strip in the plate layer to a third conductive strip in the fourth plurality of conductive strips in the second layer.

8. The capacitor of claim 7 further comprising

a second plate layer of conductive strips extending along the second direction, the first layer of conductive strips being disposed between the plate layer and the second plate layer, the second plate layer including a fifth plurality of conductive strips forming a third portion of the second node and, wherein each strip in the fourth plurality of conductive strips is next to another strip in the fourth plurality of conductive strips in the second plate layer;

a third via electrically connecting a fourth conductive strip in the second plurality of conductive strips in the first layer to a fifth conductive strip in the second plate layer;

a third plate layer, the second layer of conductive strips being disposed between the plate layer and the third plate layer; and

a fourth via electrically connecting a sixth conductive strip in the fifth plurality of conductive strips in the second layer to the third plate layer.

9. The capacitor of claim 8 wherein the third plate layer is a polysilicon or silicide layer.

10. The capacitor of claim 8 further comprising a first conductive curtain extending from the second plate layer to the third plate layer, and a second conductive curtain extending from the second plate layer to the third plate layer, the first conductive curtain and the second conductive curtain forming a fourth portion of the second node, the first conductive curtain, second plate layer, second conductive curtain, and third plate layer forming a node shield surrounding the plate layer, the first plurality of conductive strips, and the fourth plurality of conductive strips.

11. The capacitor of claim 10 further comprising a reference shield surrounding the node shield.

12. The capacitor of claim 11 wherein the reference shield includes a reference shield plate formed in a semiconductor substrate of the IC.

13. The capacitor of claim 12 wherein reference shield plate comprises an N-well.

14. The capacitor of claim 13 further including a second reference shield plate formed in a metal layer of the IC.

15. The capacitor of claim 14 wherein the metal layer is a top metal layer of the integrated circuit.

16. The capacitor of claim 14 wherein the second reference shield plate is formed in an analog ground layer of the integrated circuit.

17. The capacitor of claim 14 wherein the capacitor is located in an analog section of the integrated circuit.

18. The capacitor of claim 1 wherein the capacitor is located in an analog-to-digital converter.

19. The capacitor of claim 1 wherein the capacitor is located in a transceiver.

20. The capacitor of claim 1 wherein the integrated circuit is a field programmable gate array.